r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 456

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
Table 20.11
Notes:
UART2 bus collision
interrupt source
UART2 transmit/NACK2
interrupt source
UART2 receive/ACK2
interrupt source
Timing for transferring data
from UART receive shift
register to U2RB register
UART2 transmission output
delay
Noise filter width
Initial value of SCL2
DTC source
Storage of receive data
Read of receive data
1. If one of the bits listed below is changed, the interrupt source, the interrupt timing, and so on, change.
2. Second data transfer to the U2RB register (rising edge of SCL2 9th bit)
3. First data transfer to the U2RB register (falling edge of SCL2 9th bit)
4. Refer to Figure 20.16 STSPSEL Bit Functions .
5. Refer to Figure 20.14 Transfer to U2RB Register and Interrupt Timing .
Bits SMD0 to SMD2 in the U2MR register, the IICM bit in the U2SMR register, the IICM2 bit in the U2SMR2
register, and the CKPH bit in the U2SMR3 register.
Function
(5)
Preliminary document
Specifications in this document are tentative and subject to change.
I
2
(1, 4)
(1, 5)
(1, 5)
C Mode Functions
Start condition detection or stop condition detection
No acknowledgment detection (NACK)
Rising edge of SCL2 9th bit
Acknowledgment detection (ACK)
Rising edge of SCL2 9th bit
Acknowledgment detection (ACK)
Rising edge of SCL2 9th bit
Delay can be set
100 ns
Acknowledgment detection (ACK)
UART2
transmission
Rising edge of SCL2
9th bit
1st to 8th bits are stored in bits b0 to b7 in
the U2RB register.
The U2RB register state is read without modification.
(No clock delay)
IICM2 = 0 (NACK/ACK interrupt)
CKPH = 0
High
UART2
transmission
Falling edge of
SCL2 next to 9th bit
(With clock delay)
CKPH = 1
Low
UART2
transmission
Rising edge of SCL2
9th bit
UART2 reception
Falling edge of SCL2 9th bit
Falling edge of
SCL2 9th bit
UART2 reception
Falling edge of SCL2 9th bit
UART2
transmission
Rising edge of SCL2
9th bit
1st to 7th bits of the received data are
stored in bits b0 to b6 in the U2RB register.
8th bit is stored in bit b8 in the U2RB
register.
(No clock delay)
(UART transmit/receive interrupt)
CKPH = 0
High
20. Serial Interface (UART2)
IICM2 = 1
UART2
transmission
Falling edge of
SCL2 next to 9th bit
Falling and rising
edges of SCL2 9th
bit
UART2
transmission
Falling edge of
SCL2 next to 9th bit
1st to 8th bits are
stored in bits b0 to
b7 in the U2RB
register.
Bits b0 to b6 in the
U2RB register are
read as bits b1 to 7.
Bit b8 in the U2RB
register is read as
bit b0.
(With clock delay)
CKPH = 1
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(3)
Low
(2)