r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 503

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
Figure 21.5
Table 21.7
CEIE_ACKBT, RIE, TEIE, TIE: Bits in SIER register
CE_ADZ, ORER_AL, RDRF, TEND, TDRE: Bits in SISR register
Note:
Transmit data empty
Transmit end
Receive data full
Overrun error
Conflict error
21.3.1.3
21.3.1.4
1. Not generated in clock synchronous communication mode.
The connection between the data I/O pins and the SISDR register changes according to the combinations of the
MST bit in the SICR1 register and the MS bit in the SIMR2 register. The connection also changes according to
the BIDE bit in the SIMR2 register. Figure 21.5 shows the Association between Data I/O Pins and SISDR
Register.
The synchronous serial communication unit has five interrupt requests: transmit data empty, transmit end,
receive data full, overrun error, and conflict error. Because these interrupt requests are assigned to the
synchronous serial communication unit interrupt vector table, interrupt sources must be determined using flags.
Table 21.7 lists the Interrupt Requests of Synchronous Serial Communication Unit.
If the generation conditions in Table 21.7 are met, a synchronous serial communication unit interrupt request is
generated. Set each interrupt source to 0 by the synchronous serial communication unit interrupt routine.
• MS = 0 (clock synchronous communication mode)
• MS = 1 (4-wire bus communication mode), BIDE = 0
(standard mode), and MST = 0 (slave mode)
Interrupt Request
SISDR register
SISDR register
Preliminary document
Specifications in this document are tentative and subject to change.
Association between Data I/O Pins and SS Shift Register
Association between Data I/O Pins and SISDR Register
Interrupt Requests
Interrupt Requests of Synchronous Serial Communication Unit
Abbreviation
RXI
OEI
CEI
TXI
TEI
SSO
SSI
SSO
SSI
TIE = 1 and TDRE = 1
TEIE = 1 and TEND = 1
RIE = 1 and RDRF = 1
RIE = 1 and ORER_AL = 1
CEIE_ACKBT = 1 and CE_ADZ = 1
• MS = 1 (4-wire bus communication mode), BIDE = 0
• MS = 1 (4-wire bus communication mode) and BIDE
(standard mode), and MST = 1 (master mode)
= 1 (bidirectional mode)
SISDR register
SISDR register
21. Clock Synchronous Serial Interface
Generation Condition
(1)
Page 472 of 725
SSO
SSI
SSO
SSI