r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 407

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
19.2.4
Notes:
After Reset
1. If the U0BRG count source is changed, set the U0BRG register again.
2. The DFE bit is enabled in clock asynchronous serial I/O mode. In clock synchronous serial I/O mode, set this bit
3. When UART0 is not used, set the NCH bit to 0 (TXD pin is set to CMOS output).
4. The CKPOL bit is enabled in clock synchronous serial I/O mode.
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Address 00084h (U0C0_0), 00094h (U0C0_1)
to 0 (digital filter disabled).
Symbol UFORM
UFORM Transfer format select bit
Symbol
CKPOL CLK polarity select bit
TXEPT
Bit
CLK0
CLK1
NCH
DFE
UART0 Transmit/Receive Control Register 0 (U0C0)
—
Preliminary document
Specifications in this document are tentative and subject to change.
b7
0
U0BRG count source select bits
Reserved
RXD digital filter enable bit
Data output select bit
Transmit register empty flag
CKPOL
b6
0
Bit Name
NCH
b5
0
(3)
(4)
(2)
DFE
b4
0
(1)
TXEPT
Set to 0.
0: Data present in the transmit register
1: No data in the transmit register
0: Digital filter disabled
1: Digital filter enabled
0: TXD pin is set to CMOS output
1: TXD pin is set to N-channel open-drain output
0: Transmit data is output at the falling edge and
1: Transmit data is output at the rising edge and
0: LSB first
1: MSB first
b1 b0
0 0: f1
0 1: f8
1 0: f32
1 1: fC1
b3
1
(transmission in progress)
(transmission completed)
receive data is input at the rising edge of the
transfer clock
receive data is input at the falling edge of the
transfer clock
b2
—
0
Function
CLK1
b1
0
19. Serial Interface (UART0)
CLK0
b0
0
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R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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