r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 191

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
13. DTC
The DTC (data transfer controller) is a function that transfers data between the SFR and on-chip memory without using
the CPU. The DTC is activated by a peripheral function interrupt to perform data transfers. The DTC and CPU use the
same bus, and the DTC takes priority over the CPU in using the bus.
To control DTC data transfers, control data comprised of a transfer source address, a transfer destination address, and
operating modes are allocated in the DTC control data area. Each time the DTC is activated, the DTC reads control
data to perform data transfers.
13.1
Table 13.1
i = 0 to 3, 5, or 6, j = 0 to 23
Activation sources
Allocatable control data
Address space which can be
transferred
Maximum
number of
transfers
Maximum size
of block to be
transferred
Unit of transfers
Transfer mode
Address control Normal mode
Priority of activation sources
Interrupt
request
Transfer start
Transfer stop
Table 13.1 lists the DTC Specifications.
Overview
Item
Preliminary document
Specifications in this document are tentative and subject to change.
DTC Specifications
Normal mode
Repeat mode
Normal mode
Repeat mode
Normal mode
Repeat mode
Repeat mode
Normal mode
Repeat mode
Normal mode
Repeat mode
24 sets
256 times
255 times
256 bytes
255 bytes
Byte
On completion of the transfer causing the DTCCTj register value to change from
Fixed or incremented
Addresses of the area not selected as the repeat area are fixed or incremented.
Refer to Table 13.8 DTC Activation Sources and DTC Vector Addresses .
When the data transfer causing the DTCCTj register value to change from 1 to 0
is performed, the activation source interrupt request is generated for the CPU,
and interrupt handling is performed on completion of the data transfer.
When the data transfer causing the DTCCTj register value to change from 1 to 0
is performed while the RPTINT bit in the DTCCRj register is 1 (interrupt
generation enabled), the activation source interrupt request is generated for the
CPU, and interrupt handling is performed on completion of the transfer.
When bits DTCENi0 to DTCENi7 in the DTCENi registers are set to 1 (activation
enabled), data transfer is started each time the corresponding DTC activation
sources are generated.
• When bits DTCENi0 to DTCENi7 are set to 0 (activation disabled).
• When the data transfer causing the DTCCTj register value to change from 1 to
• When bits DTCENi0 to DTCENi7 are set to 0 (activation disabled).
• When the data transfer causing the DTCCTj register value to change from 1 to
27 sources
64 Kbytes (00000h to 0FFFFh)
Transfers end on completion of the transfer causing the DTCCTj register value to
change from 1 to 0.
1 to 0, the repeat area address is initialized and the DTRLDj register value is
reloaded to the DTCCTj register to continue transfers.
0 is completed.
0 is completed while the RPTINT bit is 1 (interrupt generation enabled).
Specification
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13. DTC