r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 210

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
13.3.9
Table 13.12
Notes:
Table 13.13
Note:
Data write
Operation
Data read
1. For the number of clock cycles required for control data write-back, refer to Table 13.11 Specifications of
2. For the number of clock cycles required for data read/write, refer to Table 13.13 Number of Clock Cycles
1. This value applies when using page access.
Vector Read
Table 13.12 shows the Operations Following DTC Activation and Required Number of Cycles for each
operation.
Table 13.13 shows the Number of Clock Cycles Required for Data Transfers.
Data is transferred as described below, when the DTBLSj (j = 0 to 23) register = N,
(1) When N = 2n (even), two-byte transfers are performed n times.
(2) When N = 2n + 1 (odd), two-byte transfers are performed n times followed by one time of one-byte
To read data from or write data to the register that to be accessed in 16-bit units, set an even value of 2 or greater
to the DTBLSj (j = 0 to 23) register.
The DTC performs accesses in 16-bit units.
Control Data Write-Back Operation .
Required for Data Transfers .
Two cycles are required for 2 bytes and an odd address.
An additional cycle is required when accessing across a page boundary. An additional cycle is also required
when using any access other than page access.
transfer.
1
Number of DTC Execution Cycles
Transfers
Preliminary document
Specifications in this document are tentative and subject to change.
Operations Following DTC Activation and Required Number of Cycles
Number of Clock Cycles Required for Data Transfers
Unit of
1-byte
2-byte
1-byte
2-byte
Read
5
Control Data
Internal RAM (During
Address
Even
DTC Transfers)
1
1
Write-back
(Note 1)
1
1
Address
Odd
2
2
Data Read
(Program
Internal
(Note 2)
ROM)
ROM
1
1
—
—
(1)
(1)
Internal
(Data
flash)
ROM
—
—
4
8
Data Write
(Note 2)
Address
SFR (Word Access)
Even
3
2
3
2
Address
Odd
Internal Operation
6
4
Page 179 of 725
1
SFR (Byte
Access)
3
6
2
4
13. DTC