r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 493

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
21.2.7
Notes:
21.2.7.1
Bits BC0 to BC3 (Bit counters)
After Reset
1. When the SSU function is used (the IICSEL bit in the IICCR register is 0 and the ICE bit in the SICR1 register is
2. For the settings of bits CPHS and CPOS_WAIT, refer to 21.3.1.2 Association between Transfer Clock
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Address 000E8h (SIMR1_0)
In the SIMR1 register, the bit functions differ depending on the SSU function and the I
0), writing has no effect.
Polarity, Phase, and Data .
When the MS bit in the SIMR2 register is 0 (clock synchronous communication mode), set the CPHS bit to 0 and
the CPOS_WAIT bit to 0.
The state of the shift register during transmission/reception can be read.
Symbol
CPOS_WAIT Clock select bit
Bit
SI Mode Register 1 (SIMR1)
Symbol
CPHS
MLS
BC0
BC1
BC2
BC3
—
Preliminary document
Specifications in this document are tentative and subject to change.
SSU Function
MLS
b7
0
Bit counters
(1)
Nothing is assigned. The write value must be 1. The read value is 1.
Transfer clock phase select bit
MSB first/LSB first select bit
CPOS_WAIT
b6
0
Bit Name
(2)
CPHS
b5
0
b4
—
1
(2)
0: Data change at odd edge
1: Data change at even edge
0: High when clock stops
1: Low when clock stops
0: Data transfer with MSB first
1: Data transfer with LSB first
BC3
b3 b2 b1 b0
0 0 0 0: Remaining 16 bits
0 0 0 1: Remaining 1 bit
0 0 1 0: Remaining 2 bits
0 0 1 1: Remaining 3 bits
0 1 0 0: Remaining 4 bits
0 1 0 1: Remaining 5 bits
0 1 1 0: Remaining 6 bits
0 1 1 1: Remaining 7 bits
1 0 0 0: Remaining 8 bits
1 0 0 1: Remaining 9 bits
1 0 1 0: Remaining 10 bits
1 0 1 1: Remaining 11 bits
1 1 0 0: Remaining 12 bits
1 1 0 1: Remaining 13 bits
1 1 1 0: Remaining 14 bits
1 1 1 1: Remaining 15 bits
b3
0
(data download at even edge)
(data download at odd edge)
BC2
b2
0
21. Clock Synchronous Serial Interface
Function
BC1
b1
0
2
C bus function.
BC0
b0
0
Page 462 of 725
R/W
R/W
R/W
R/W
—
R
R
R
R