r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 270

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
15.5
(1) Timer RJ stops counting after a reset. Start the count only after setting the value in the timer.
(2) After 1 (count starts) is written to the TSTART bit in the TRJCR register while the count is stopped, the
(3) In event counter mode, set the TSTART bit in the TRJCR register to 1 (count starts) and then input an external
(4) In pulse width/pulse period measurement modes, bits TEDGF and TUNDF in the TRJCR register used are set
(5) The period data of the input pulse = (initial value set in the counter – value read from the read-out buffer) + 1
(6) Insert NOP instructions between writing to and reading from registers associated with the TRJ counter while
(7) When the TSTART bit in the TRJCR register is 1 (count starts) or the TCSTF bit is 1 (count in progress),
(8) When the operating mode is switched, the values of bits TEDGF and TUNDF are undefined. Write 0 (no
(9) When bits TSTART and TCSTF are 0 (count stops), switch to module standby mode.
(10) For pulse width measurement mode or pulse period measurement mode, perform settings in the following
(11) In pulse period measurement mode, the processing on completion of the first measurement is invalid (the
(12) If the TRJ register is set to 0000h, the timer RJ interrupt request will remain in the enabled state. This interrupt
(13) Connection between external INT input and timer RJ_0
(14) Connection between event input from timer RC and timer RJ_0
(15) In pulse width measurement mode, do not select an event from the event link controller (ELC) as the count
(16) Set the TOPCR bit in the TRJIOC register after other SFR settings are completed.
Note:
1. Set the registers associated with timer RJ.
2. Set the TSTART bit to 1 (count starts).
3. Input an external event.
• INT1
• Timer RC_0
TCSTF bit in the TRJCR register remains 0 (count stops) for three cycles of the count source. Do not access
the registers associated with timer RJ
The count is started from the first active edge of the count source after the TCSTF bit is set to 1.
After 0 (count stops) is written to the TSTART bit during a count operation, the TCSTF bit remains 1 for three
cycles of the count source. When the TCSTF bit is set to 0, the count is stopped. Do not access the registers
associated with timer RJ
event.
Number of counted events = initial value in the counter – value in the counter on completion of the valid event
+ 1
to 0 by writing 0 by a program, but remain unchanged even if 1 is written to these bits. If a bit manipulation
instruction is used to set the TRJCR register, bits TEDGF and TUNDF may be erroneously set to 0 depending
on the timing, even when the TEDGF bit is set to 1 (active edge received) and the TUNDF bit is set to 1
(underflow) during execution of the instruction.
In order to avoid this, set bits TEDGF and TUNDF to 1 using the MOV instruction.
the counter is stopped.
allow at least three cycles of the count source clock between writes when writing to the TRJ register
successively.
active edge received) to the TEDGF bit and 0 (no underflow) to the TUNDF bit before starting timer RJ count.
order:
measured value is valid for the second and subsequent times)
request is used to perform a related operation with the hardware LIN and the event link controller (ELC) once.
source. During coordinated operation with the ELC (bits TCK2 to TCK0 in the TRJMR register = 101b), set
the TSTART bit in the TRJCR register to 1 before inputting an event from the ELC. After the count of the
valid event is completed, set the TSTART bit to 0.
Notes on Timer RJ
1. Registers associated with timer RJ: TRJ, TRJCR, TRJIOC, and TRJMR

Preliminary document
Specifications in this document are tentative and subject to change.
timer RJ_0

timer RJ_0
(1)
other than the TCSTF bit until this bit is set to 0.
(1)
other than the TCSTF bit until this bit is set to 1 (count in progress).
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15. Timer RJ