r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 64

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
5.
5.1
5.2
Table 5.1
Notes:
5.2.1
Processor Mode Register 0
Processor Mode Register 1
Protect Register
Option Function Select Register 2
Option Function Select Register
This chapter describes system control functions, such as ID code checking, register access protection, and option
functions.
Table 5.1 lists the Register Configuration for System Control.
PM03 Bit (Software reset bit)
After Reset
Bit
b0
b1
b2
b3
b4
b5
b6
b7
System Control
1. The OFS2 register is allocated in the flash memory, not in the SFRs. Set appropriate values as ROM data by a
2. The OFS register is allocated in the flash memory, not in the SFRs. Set appropriate values as ROM data by a
Address 00004h
Set the PRC1 bit in the PRCR register to 1 (write enabled) before rewriting the PM0 register.
When the PM03 bit is set to 1, the entire MCU is reset. The read value is 0.
Symbol
program.
Do not perform any additional writes to the OFS2 register. Erasing the block including the OFS2 register sets
the OFS2 register to FFh.
program.
Do not perform any additional writes to the OFS register. Erasing the block including the OFS register sets the
OFS register to FFh.
Overview
Registers
Symbol
Bit
PM03
Processor Mode Register 0 (PM0)
—
—
—
—
—
—
—
Preliminary document
Specifications in this document are tentative and subject to change.
Register Configuration for System Control
Register Name
b7
—
0
Reserved
Software reset bit
Nothing is assigned. The write value must be 0. The read value is 0.
b6
—
0
Bit Name
b5
—
0
b4
—
0
Symbol
PRCR
OFS2
PM0
PM1
OFS
Set to 0.
0: State is retained
1: Reset is generated
PM03
b3
0
After Reset
10000000b
(Note 1)
(Note 2)
00h
00h
b2
—
0
Function
b1
—
0
0FFDBh
Address
0FFFFh
00004h
00005h
00007h
b0
—
0
5. System Control
Access Size
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8
8
8
8
8
R/W
R/W
R/W
—