r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 514

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
Figure 21.13
21.3.3.1
Figure 21.13 shows the Initialization in 4-Wire Bus Communication Mode. Before data transmission/reception,
set the TE_NAKIE bit in the SIER register to 0 (transmission disabled) and the RE_STIE bit to 0 (reception
disabled) for initialization.
To change the communication mode or the communication format, set the TE_NAKIE bit to 0 and the
RE_STIE bit to 0 before making the change.
Even if the RE_STIE bit is set to 0, the contents of bits RDRF and ORER_AL and the SIRDR register are
retained.
After slave receive operation, SCS may be asserted when the mode is switched to master mode even though no
transfer start condition is written.
Note:
SIER register
SIMR1 register
SIMR2 register
SICR1 register
SIER register
1. To set the ORER_AL bit to 0, write 0 after reading it as 1.
Preliminary document
Specifications in this document are tentative and subject to change.
Initialization in 4-Wire Bus Communication Mode
Initialization in 4-Wire Bus Communication Mode
SSBR register Set bits BS0 to BS3
SISR register ORER_AL bit  0
SICR1 register Set MST bit
SIMR2 register MS bit  1
RE_STIE bit  0
TE_NAKIE bit  0
Set CPHS bit
Set CPOS_WAIT bit
MLS bit  0
SCKS bit  1
Set bits SOOS, CSS0, CSS1,
BIDE
Set bits CKS0 to CKS2
Set RCVD bit
RE_STIE bit  1 (receive)
TE_NAKIE bit  1 (transmit)
Set bits RIE, TEIE, and TIE
Start
End
(1)
Reception disabled
Transmission disabled
SSU data transfer length setting
Mode selected (4-wire system communication mode)
Clock phase selected (data change at odd/even edge)
Clock state selected (high/low when clock stops)
MSB first selected
Master/slave mode selected
SSCK pin selected (port function)
SSCK pin open-drain output selected
SCS pin I/O setting
Bidirectional mode setting
Clock period setting
Receive disable bit setting
Overrun error flag cleared
Transmission/reception enable setting
Interrupt enable setting
21. Clock Synchronous Serial Interface
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