r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 425

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
Table 20.1
Notes:
Clock
synchronous
serial I/O
mode
1. When an external clock is selected, the requirements must be met in either of the following states:
2. If an overrun error occurs, the receive data in the U2RB register will not be updated (the previous data will be
- The external clock is held high when the CKPOL bit in the U2C0 register is set to 0 (transmit data is output at
- The external clock is held low when the CKPOL bit is set to 1 (transmit data is output at the rising edge and
read).
the falling edge and receive data is input at the rising edge of the transfer clock)
receive data is input at the falling edge of the transfer clock)
Preliminary document
Specifications in this document are tentative and subject to change.
UART2 Specifications (1)
Pins used
Noise filter
Transfer data format
Transfer clock
Transmit/receive
control
Transmit start
conditions
Receive start
conditions
Interrupt request
generation timing
Error detection
Selectable functions
Item
• TXD2: Transmit data (output)
• RXD2: Receive data (input)
• CLK2: Transfer clock (master: output, slave: input)
• CTS2: Transmit request signal (input)
• RTS2: Receive request signal (output)
10 ns noise filter for CLK2 and RXD2 input
Transfer data length: 8 bits
• The CKDIR bit in the U2MR register is set to 0 (internal clock): fj/(2(n + 1))
• The CKDIR bit is set to 1 (external clock): Input from the CLK2 pin
CTS function, RTS function, or CTS/RTS function disabled selectable
To start transmission, the following requirements must be met:
• The TE bit in the U2C1 register is set to 1 (transmission enabled).
• The TI bit in the U2C1 register is set to 0 (data present in the U2TB
• If the CTS function is selected, input to the CTS2 pin is low.
To start reception, the following requirements must be met:
• The RE bit in the U2C1 register is set to 1 (reception enabled).
• The TE bit in the U2C1 register is set to 1 (transmission enabled).
• The TI bit in the U2C1 register is set to 0 (data present in the U2TB
• If the CTS function is selected, input to the CTS2 pin is low.
For transmission, one of the following conditions can be selected.
For reception
• Overrun error
• CLK polarity selection
• LSB first/MSB first selection
• Continuous receive mode selection
• Serial data logic switching
fj = f1, f8, f32, or fC1
n = Value set in the U2BRG register (00h to FFh)
register).
register).
Transfer data I/O can be selected to occur synchronously with the rising or
falling edge of the transfer clock.
Whether transmitting or receiving data begins with bit 0 or begins with bit 7
can be selected.
A function that enables reception immediately upon reading the U2RB
register can be selected.
This function inverts the logic value of the transmit/receive data.
-The U2IRS bit in the U2C1 register is set to 0 (transmit buffer empty):
-The U2IRS bit is set to 1 (transmission completed):
When data is transferred from the UART2 receive register to the U2RB
register (at completion of reception).
This error occurs if the serial interface starts receiving the next unit of data
before reading the U2RB register and receives the 7th bit of the next unit
of data.
When data transmission from the UART2 transmit register is completed.
When data is transferred from the U2TB register to the UART2 transmit
register (at start of transmission).
(2)
Specification
20. Serial Interface (UART2)
(1)
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