r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 470

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
Figure 20.25
20.3.4
When the multiprocessor communication function is used, data transmission/reception can be performed
between a number of processors sharing communication lines by clock asynchronous serial I/O mode (UART
mode), in which a multiprocessor bit is added to the data. For multiprocessor communication, each receiving
station is addressed by a unique ID code. The serial communication cycle consists of two component cycles; an
ID transmission cycle for specifying the receiving station, and a data transmission cycle for the specified
receiving station. The multiprocessor bit is used to differentiate between the ID transmission cycle and the data
transmission cycle. When the multiprocessor bit is set to 1, the cycle is an ID transmission cycle; when the
multiprocessor bit is set to 0, the cycle is a data transmission cycle. Figure 20.25 shows an Inter-Processor
Communication Example Using Multiprocessor Format (Data Transmission to Receiving Station A).
The transmitting station first sends the ID code of the receiving station to perform communication as
communication data with a 1 multiprocessor bit added. It then sends transmit data as communication data with
a 0 multiprocessor bit added.
When communication data in which the multiprocessor bit is 1 is received, the receiving station compares that
data with its own ID. If they match, the data to be sent next is received. If they do not match, the receive station
continues to skip communication data until data in which the multiprocessor bit is 1 is again received.
UART2 uses the MPIE bit in the U2SMR5 register to implement this function. When the MPIE bit is set to 1,
data transfer from the UART2 receive register to the U2RB register, receive error detection, and the settings of
the status flags, the RI bit in the U2C1 register, bits FER and OER in the U2RB register, are disabled until data
in which the multiprocessor bit is 1 is received. On receiving a receive character in which the multiprocessor bit
is 1, the MPRB bit in the U2RB register is set to 1 and the MPIE in the U2SMR5 register bit is set to 0, thus
normal reception is resumed.
When the multiprocessor format is specified, the parity bit specification is invalid. All other bit settings are the
same as those in normal clock asynchronous serial I/O mode (UART mode). The clock used for multiprocessor
communication is the same as that in normal clock asynchronous serial I/O mode (UART mode).
Table 20.13 lists the Registers and Settings Used by Multiprocessor Communication Function
Multiprocessor Communication Function
Serial data
Preliminary document
Specifications in this document are tentative and subject to change.
Inter-Processor Communication Example Using Multiprocessor Format
(Data Transmission to Receiving Station A)
Transmitting
Receiving
(ID = 01h)
station A
station
MPRB: Multiprocessor bit
ID transmission cycle
= receiving station
specification
Receiving
(ID = 02h)
(MPRB = 1)
station B
01h
Communication line
Data transmission cycle
= data transmission to
receiving station
specified by ID
(ID = 03h)
Receiving
station C
AAh
(MPRB = 0)
Receiving
(ID = 04h)
station D
20. Serial Interface (UART2)
(1)
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