r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 665

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
26.5
Table 26.4
Operating mode
Rewrite control program
allocatable areas
Rewrite control program
executable areas
Rewritable areas
Software command
restrictions
Mode after programming
or block erasure or after
entering erase-suspend
CPU and DTC state
during programming and
block erasure
Flash memory status
detection
Conditions for entering
erase-suspend
CPU clock
In CPU rewrite mode, the user ROM area can be rewritten by executing software commands from the CPU.
Therefore, the user ROM area can be rewritten directly while the MCU is mounted on a board without using a
ROM programmer. Execute the software command only to blocks in the user ROM area.
The flash module has an erase-suspend function which halts the erase operation temporarily during an erase
operation in CPU rewrite mode. During erase-suspend, the flash memory can be read or programmed.
Erase-write 0 mode (EW0 mode) and erase-write 1 mode (EW1 mode) are available in CPU rewrite mode.
Table 26.4 lists the Differences between EW0 Mode and EW1 Mode.
CPU Rewrite Mode
Item
Preliminary document
Specifications in this document are tentative and subject to change.
Differences between EW0 Mode and EW1 Mode
Single-chip mode
User ROM and data flash
RAM (The rewrite control program must
be transferred before being executed.)
However, the program can be executed
in the program ROM area when rewriting
the data flash area.
Read array mode
The CPU and DTC operate.
Read bits FST7, FMT5, and FMT4 in the
FST register by a program.
• Set bits FMR20 and FMR21 in the
• Set bits FMR20 and FMR22 in the
32 MHz
User ROM and data flash
FMR2 register to 1 by a program.
FMR2 register to 1 and the enabled
maskable interrupt is generated.
EW0 Mode
—
32 MHz
Single-chip mode
User ROM and data flash
User ROM or RAM
User ROM and data flash
(However, blocks which contain the rewrite
control program are excluded.)
Program and block erase commands
(Cannot be executed to any block which
contains the rewrite control program.)
Read array mode
• The CPU or DTC operates while the data
• The CPU or DTC is put in a hold state while
Read bits FST7, FST5, and FST4 in the FST
register by a program.
• Set bits FMR20 and FMR21 in the FMR2
• Set bits FMR20 and FMR22 in the FMR2
flash area is being programmed or block
erased.
the program ROM area is being programmed
or block erased (I/O ports retain the state
before the command execution).
register to 1 by a program (while rewriting
the data flash area).
register to 1 and the enabled maskable
interrupt is generated.
EW1 Mode
26. Flash Memory
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