r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 145
r5f21368sdfp
Manufacturer Part Number
r5f21368sdfp
Description
Renesas Mcu R8c Family / R8c/3xt-a Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.R5F21368SDFP.pdf
(760 pages)
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Part Number:
r5f21368sdfp#V0
Manufacturer:
Renesas Electronics America
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Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
10.4
10.4.1
10.4.2
10.4.3
The CPU clock is stopped in wait mode. Thus the CPU, which operates using the CPU clock, and the watchdog
timer when count source protection mode is disabled are stopped. The XIN clock, XCIN clock, and on-chip
oscillator clocks are not stopped, so the peripheral functions that use these clocks continue operating.
When the CM02 bit in the CM0 register is 1 (peripheral function clock stops in wait mode), power consumption
is reduced because f1, f2, f4, f8, and f32 are stopped in wait mode.
The MCU enters wait mode when the WAIT instruction is executed or the CM30 bit in the CM3 register is set
to 1 (MCU enters wait mode).
When the CM40 bit in the CM4 register is 1 (system clock selected as on-chip oscillator), set the OCD1 bit in
the OCD register to 0 (oscillation stop detection disabled) before executing the WAIT instruction or set the
CM30 bit to 1 (MCU enters wait mode).
If the MCU enters wait mode while the OCD1 bit is 1 (oscillation stop detection enabled), power consumption
is not reduced because the CPU is not stopped.
To enter wait mode or stop mode while the FMR27 bit in the FMR2 register is 1 (low-current-consumption read
mode enabled), set bits CM37 and CM36 in the CM3 register to 00b (MUC exits using the CPU clock used
immediately before entering wait mode or stop mode) and the CM35 bit in the CM3 register to 0 (settings of
CM06 bit in CM0 register and bits CM16b and CM17 in CM1 register enabled).
The I/O ports retain the states immediately before the MCU enters wait mode.
Wait Mode
Peripheral Function Clock Stop Function
Entering Wait Mode
Pin States in Wait Mode
Preliminary document
Specifications in this document are tentative and subject to change.
10. Power Control
Page 114 of 725
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