r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 513

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
21.3.3
In 4-wire bus communication mode, a 4-wire bus consisting of a clock line, a data input line, a data output line,
and a chip select line is used for communication. This mode includes a bidirectional mode in which the data
input line and data output line function as a single pin.
The data input line and output line change according to the settings of the MST bit in the SICR1 register and the
BIDE bit in the SIMR2 register. For details, refer to 21.3.1.3 Association between Data I/O Pins and SS Shift
Register. In this mode, the association between clock polarity, phase, and data are set using bits CPOS_WAIT
and CPHS in the SIMR1 register. For details, refer to 21.3.1.2 Association between Transfer Clock Polarity,
Phase, and Data.
The chip select line controls output for the master device, and it controls input for the slave device. For the
master device, the chip select line controls output of the SCS pin or controls output of an I/O port when the
CSS1 bit in the SIMR2 register is set to 1. For the slave device, the chip select line sets the SCS pin to function
as an input pin when bits CSS1 and CSS0 in the SIMR2 register are set to 01b.
In 4-wire bus communication mode, the MLS bit in the SIMR1 register is set to 0 and communication is
performed with MSB first.
4-Wire Bus Communication Mode
Preliminary document
Specifications in this document are tentative and subject to change.
21. Clock Synchronous Serial Interface
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