r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 453

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
Figure 20.13
20.3.2.7
When the DF2EN bit in the U2RXDF register is set to 1 (RXD2 digital filer enabled), the RXD2 input signal is
loaded internally via the digital filter circuit for noise reduction. The noise canceller consists of three cascaded
latch circuits and a match detection circuit. The RXD2 input signal is sampled on the internal basic clock (baud
rate clock: the clock with count source divided by the value set in the U2BRG register) with a frequency 16
times the bit rate. It is recognized as a signal and the level is passed forward to the next circuit when the three
latch outputs match. When the outputs do not match, the previous value is retained.
In other words, when the level changes within three clocks, the change is recognized not as a signal change but
as noise.
Figure 20.13 shows the RXD2 Digital Filter Circuit Block Diagram.
input signal
Baud rate
RXD2
clock
Preliminary document
Specifications in this document are tentative and subject to change.
RXD2 Digital Filter Select Function
RXD2 Digital Filter Circuit Block Diagram
D
Q
D
Q
D
Q
(U2RXDF register)
detection
Match
circuit
DF2EN bit
0
1
20. Serial Interface (UART2)
Internal RXD2
input signal
Page 422 of 725