r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 517

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
21.3.3.3
Figure 21.15 shows an Operation Example during Data Reception (4-Wire Bus Communication Mode, 8-Bit
SSU Data Transfer Length). During data reception, the synchronous serial communication unit operates as
described below. (The data transfer length can be set from 8 to 16 bits using the SSBR register.)
When the MCU is set as the master device, it outputs a synchronous clock and inputs data. When the MCU is
set as a slave device, it outputs data synchronized with the input clock while the SCS pin input is held low.
When the MCU is set as the master device, it outputs a receive clock and reception is started by performing a
dummy read of the SIRDR register.
After 8 bits of data are received, the RDRF bit in the SISR register is set to 1 (data present in the SIRDR
register) and receive data is stored in the SIRDR register. If the RIE bit in the SIER register is 1 (RXI and OEI
interrupt requests enabled) at this time, an RXI interrupt request is generated. When the SIRDR register is read,
the RDRF bit is automatically set to 0 (no data in the SIRDR register).
When the MCU is set as the master device and reception completes, set the RCVD bit in the SICR1 register to 1
(receive operation is completed after 1 byte of data is received) before reading the [last frame - 1] of the receive
data. With this setting, the synchronous serial communication unit outputs a receive clock for the [last frame]
and then stops. After that, set the RE_STIE bit in the SIER register to 0 (reception disabled) and the RCVD bit
to 0 (receive operation continues after 1-byte data is received), and then read the receive data. When the SIRDR
register is read while the RE_STIE bit in the SIER register is set to 1 (receive enabled), a receive clock is output
again.
When the 8th clock rises while the RDRF bit is 1, the ORER_AL bit in the SISR register is set to 1 (overrun
error: OEI) and the operation is stopped. When the ORER_AL bit is 1, reception cannot be performed. Confirm
that the ORER_AL bit is 0 before restarting reception.
The timing at which bits RDRF and ORER_AL are set to 1 varies depending on the setting of the CPHS bit in
the SIMR1 register. Figure 21.15 shows this timing. If the CPHS bit is set to 1 (data download at odd edge),
care must be taken when reception is completed because these bits are set to 1 at some point during the frame.
The sample flowchart is the same as that for clock synchronous communication mode (refer to Figure 21.10
Sample Flowchart for Data Reception (MST = 1) (Clock Synchronous Communication Mode)).
Notes when Overrun Error Occurs
After an overrun error occurs, use the following procedure to cancel the overrun error state:
(1) Transfer operation is completed (confirm that module selection is negated  A conflict error occurs in
(2) Read the last received data (data before an overrun error occurs).
(3) Clear the overrun error flag (a conflict error also occurs in slave mode).
slave mode).
Preliminary document
Specifications in this document are tentative and subject to change.
Data Reception
21. Clock Synchronous Serial Interface
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