r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 421

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
Figure 19.8
19.3.2.3
19.3.2.4
RXD
When the DFE bit in the U0C0 register is 1 (digital filter enabled), the RXD input is latched internally through
the digital filter circuit for noise cancellation. The noise canceller consists of three cascaded latch circuits and a
match detection circuit. When the RXD input is sampled on the base clock with frequency of 16 times the
transfer rate and three latch outputs match, the level is passed forward to the next circuit. When they do not
match, the previous level is retained.
That is, if the RXD input retains the same level for three clocks or more, it is recognized as a signal. If not, it is
recognized as noise.
Figure 19.8 shows the RXD Digital Filter Block Diagram.
If communication is aborted or a communication error occurs while transmitting or receiving in UART mode,
follow the procedure below:
(1) Set the TE bit in the U0C1 register to 0 (transmission disabled) and the RE bit to 0 (reception disabled).
(2) Set bits SMD2 to SMD0 in the U0MR register to 000b (serial interface disabled).
(3) Set bits SMD2 to SMD0 in the U0MR register to 100b (UART mode, transfer data 7 bits long), 101b
(4) Set the TE bit in the U0C1 register to 1 (transmission enabled) and the RE bit to 1 (reception enabled).
(UART mode, transfer data 8 bits long), or 110b (UART mode, transfer data 9 bits long).
Sampling clock
RXD Digital Filter
Preliminary document
Specifications in this document are tentative and subject to change.
RXD Digital Filter Block Diagram
Dealing with Communication Errors
D
Latch
C
Q
D
Latch
C
Q
D
Latch
C
Q
detection
Match
circuit
in U0C0
DFE bit
register
19. Serial Interface (UART0)
Internal RXD input
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