r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 508

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
Figure 21.9
21.3.2.3
SICR1 register
• MS = 0 (clock synchronous communication mode), CPHS = 0 (data download at even edge),
Figure 21.9 shows an Operation Example during Data Reception (Clock Synchronous Communication Mode,
8-Bit SSU Data Transfer Length). During data reception, the synchronous serial communication unit operates
as described below. (The data transfer length can be set from 8 to 16 bits using the SSBR register.)
When the MCU is set as the master device, it outputs a synchronous clock and inputs data. When the MCU is
set as a slave device, it inputs data synchronized with the input clock.
When the MCU is set as the master device, it outputs a receive clock and reception is started by performing a
dummy read of the SIRDR register.
After 8 bits of data are received, the RDRF bit in the SISR register is set to 1 (data present in the SIRDR
register) and receive data is stored in the SIRDR register. If the RIE bit in the SIER register is 1 (RXI and OEI
interrupt requests enabled) at this time, an RXI interrupt request is generated. When the SIRDR register is read,
the RDRF bit is automatically set to 0 (no data in the SIRDR register).
When the MCU is set as the master device and reception completes, set the RCVD bit in the SICR1 register to 1
(receive operation is completed after 1 byte of data is received) before reading the [last frame - 1] of the receive
data. With this setting, the synchronous serial communication unit outputs a receive clock for the [last frame]
and then stops. After that, set the RE_STIE bit in the SIER register to 0 (reception disabled) and the RCVD bit
to 0 (receive operation continues after the 1 byte of data is received), and then read the last received data from
the SIRDR register. If the SIRDR register is read while the RE_STIE bit is 1 (reception enabled), a receive
clock is output again.
When the 8th clock rises while the RDRF bit is 1, the ORER_AL bit in the SISR register is set to 1 (overrun
error: OEI) and the operation is stopped. While the ORER_AL bit is 1, reception cannot be performed. Confirm
that the ORER_AL bit is 0 before restarting reception. If an overrun error occurs, the data received in the frame
where the error has occurred is discarded.
Figure 21.10 shows a Sample Flowchart for Data Reception (MST = 1) (Clock Synchronous Communication
Mode).
SISR register
CPOS_WAIT = 0 (high when clock stops), MLS = 1 (LSB-first transfer), and BS3 to BS0 = 1000b (8 bits)
RCVD bit in
RDRF bit in
processing
Program
SSCK
SSI
Preliminary document
Specifications in this document are tentative and subject to change.
Data Reception
Operation Example during Data Reception (Clock Synchronous Communication
Mode, 8-Bit SSU Data Transfer Length)
Dummy read
SIRDR register
RXI interrupt request generated
b0
1
One frame
Read data from
SIRDR register
b7
8
b0
RXI interrupt request generated
1
One frame
BS0 to BS3: Bits in SSBR register
CPHS, CPOS_WAIT, MLS: Bits in SIMR1 register
MS: Bit in SIMR2 register
Set RCVD bit to 1
b7
8
21. Clock Synchronous Serial Interface
b0
1
Last frame
Read data from
SIRDR register
RXI interrupt
request
generated
Clock stops
b7
8
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