r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 78

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
6.2.4
Notes:
LVDAS Bit (Voltage detection 0 circuit start bit)
After Reset
1. The OFS register is allocated in the flash memory, not in the SFRs. Set appropriate values as ROM data by a
2. The same voltage detection 0 level selected by bits VDSEL0 and VDSEL1 is set in both the voltage monitor 0
3. Set the LVDAS bit to 0 (voltage monitor 0 reset enabled after reset) to use the power-on reset or voltage monitor
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Address 0FFFFh
program. Do not perform any additional writes to the OFS register. Erasing the block including the OFS register
sets the OFS register to FFh. The value of the OFS register is FFh at shipment of blank products. After
programming, the value is the same as that programmed by the user. At shipment of factory-programmed
products, the value of the OFS register is the same as that set in a program by the user.
reset and power-on reset functions.
0 reset.
For an example of the OFS register settings, refer to 5.6.1 Option Function Select Area Setting Examples.
The Vdet0 voltage monitored in the voltage detection 0 circuit is selected by bits VDSEL0 and VDSEL1.
Symbol CSPROINI LVDAS
CSPROINI Count source protection mode
ROMCP1 ROM code protect bit
ROMCR
VDSEL0
VDSEL1
Bit
WDTON
Symbol
LVDAS
Option Function Select Register (OFS)
—
Preliminary document
Specifications in this document are tentative and subject to change.
b7
Watchdog timer start select bit 0: Watchdog timer automatically starts after reset
Reserved
ROM code protect disable bit
Voltage detection 0 level
select bits
Voltage detection 0 circuit
start bit
after reset select bit
b6
Bit Name
VDSEL1 VDSEL0 ROMCP1 ROMCR
b5
User Setting Value
b4
1: Watchdog timer stops after reset
Set to 1.
0: ROM code protect disabled
1: ROMCP1 bit enabled
0: ROM code protect enabled
1: ROM code protect disabled
0: Voltage monitor 0 reset enabled after reset
1: Voltage monitor 0 reset disabled after reset
0: Count source protect mode enabled after reset
1: Count source protect mode disabled after reset
b5 b4
0 0: 3.80 V (typ.) selected (Vdet0_3)
0 1: 2.85 V (typ.) selected (Vdet0_2)
1 0: 2.35 V (typ.) selected (Vdet0_1)
1 1: 1.90 V (typ.) selected (Vdet0_0)
b3
(1)
b2
Function
b1
—
WDTON
b0
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6. Resets
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W