r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 77

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
6.2.3
Note:
Bits WDTRCS0 and WDTRCS1
(Watchdog timer refresh acceptance period set bits)
After Reset
1. The OFS2 register is allocated in the flash memory, not in the SFRs. Set appropriate values as ROM data by a
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Address 0FFDBh
program. Do not perform any additional writes to the OFS2 register. Erasing the block including the OFS2
register sets the OFS2 register to FFh. The value of the OFS2 register is FFh at shipment of blank products. After
programming, the value is the same as that programmed by the user. At shipment of factory-programmed
products, the value of the OFS2 register is the same as that set in a program by the user.
For an example of the OFS2 register settings, refer to 5.6.1 Option Function Select Area Setting Examples.
These bits are used to select the refresh acceptance period as a percentage. Note that the period from the start of
counting to underflow is 100%.
For details, refer to 8.3.1.1 Refresh Acceptance Period.
Symbol
WDTRCS0 Watchdog timer refresh acceptance
WDTRCS1
WDTUFS0 Watchdog timer underflow period set
WDTUFS1
Bit
Symbol
Option Function Select Register 2 (OFS2)
—
—
—
—
Preliminary document
Specifications in this document are tentative and subject to change.
b7
—
bits
period set bits
Reserved
b6
—
Bit Name
b5
—
User Setting Value
b4
—
Set to 1.
b1 b0
b3 b2
0 0: 03FFh
0 1: 0FFFh
1 0: 1FFFh
1 1: 3FFFh
0 0: 25%
0 1: 50%
1 0: 75%
1 1: 100%
WDTRCS1 WDTRCS0 WDTUFS1 WDTUFS0
b3
(1)
b2
Function
b1
Page 46 of 725
b0
6. Resets
R/W
R/W
R/W
R/W
R/W
R/W