r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 150

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
Figure 10.4
10.5.3
A reset or a peripheral function interrupt is used to exit stop mode.
Figure 10.4 shows the Time from Stop Mode to Interrupt Routine Execution.
To use a peripheral function interrupt to exit stop mode, the following items must be set before setting the
CM10 bit in the CM1 register to 1:
(1) Set the interrupt priority level in bits ILVL0 to ILVL2 in the interrupt priority level registers for the
(2) Set the I flag in the FLG register to 1 (maskable interrupt enabled).
(3) Operate the peripheral function to be used to exit stop mode.
When a peripheral function interrupt is used to exit stop mode, the interrupt sequence is executed after the
interrupt request is generated and the supply of the CPU clock starts.
The CPU clock when a peripheral function interrupt is used to exit stop mode is a divide-by-8 of the clock used
immediately before entering stop mode. When entering stop mode, set the CM35 bit in the CM3 register to 0
(settings of CM06 bit in CM0 register and bits CM16 and CM17 in CM1 register enabled).
(flash memory operates)
mode
Stop
(flash memory stops)
FMR0 Register
peripheral function interrupts that are used to exit stop mode.
Also, set 000b (interrupt disabled) in bits ILVL0 to ILVL2 in the interrupt priority level registers for the
peripheral function interrupts that are not to be used to exit stop mode.
FMSTP Bit
Exiting Stop Mode
Interrupt request generated
Internal power
100 s (max.)
stabilization
0
1
Preliminary document
Specifications in this document are tentative and subject to change.
Time from Stop Mode to Interrupt Routine Execution
time
T0
Oscillation time of CPU clock
source used immediately
before stop mode
Stabilization Time
100 s (max.)
100 s (max.)
Internal Power
T1
(T0)
 1 cycle + 60 s (max.)
Period of system clock
Period of system clock
activation sequence
Activation (T2)
Flash memory
Flash Memory
Time until
 1 cycle
T2
Period of CPU clock
restart sequence
Same as above
Supply (T3)
CPU Clock
 2 cycles
CPU clock
Time until
T3
Period of CPU clock
Same as above
Sequence (T4)
 20 cycles
sequence
Interrupt
Interrupt
Time for
T4
The total of T0 to T4
amounts to the time
from stop mode to
interrupt routine
execution.
Remarks
10. Power Control
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