r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 208

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
Figure 13.10
13.3.6
13.3.7
When the CHNE bit in the registers DTCCR0 to DTCCR22 are 1 (chain transfers enabled), multiple data
transfers can be continuously performed by one activation source. Figure 13.10 shows a Flow of Chain
Transfers.
When the DTC is activated, one control data is selected according to the data read from the DTC vector address
corresponding to the activation source, and the selected control data is read from the DTC control data area.
When the CHNE bit for the control data is 1, the next control data immediately following the current control
data is read and transferred after the current transfer is completed. This operation is repeated until the data
transfer with the control data for which the CHNE bit is 0 (chain transfers disabled) is completed.
Set the CHNE bit in the DTCCR23 register to 0 (chain transfers disabled).
When the data transfer causing the DTCCTj (j = 0 to 23) register value to change to 0 is performed in normal
mode, and when the data transfer causing the DTCCTj register value to change to 0 is performed while the
RPTINT bit in the DTCCRj register is 1 (interrupt generation enabled) in repeat mode, the interrupt request
corresponding to the activation source is generated for the CPU during DTC operation. However, no interrupt
request is generated for the CPU when the activation source is SSU/I
memory ready status.
Interrupt requests for the CPU are affected by the I flag or interrupt control register. In chain transfers, whether
the interrupt request is generated or not is determined either by the number of transfer times specified for the
first type of the transfer or the RPTINT bit. When an interrupt request is generated for the CPU, the bit among
bits DTCENi0 to DTCENi7 in the DTCENi (i = 0 to 3, 5, or 6) registers corresponding to the activation source
are set to 0 (activation disabled).
Chain Transfers
Interrupt Sources
Preliminary document
Specifications in this document are tentative and subject to change.
Flow of Chain Transfers
CHNE: Bit in DTCCRj register
DTC control data area
Control data 1
Control data 2
CHNE = 1
CHNE = 0
Write back control data 1
Write back control data 2
DTC activation source
End of DTC transfers
Read control data 1
Read control data 2
Read DTC vector
Transfer data
Data transfer
generation
2
C bus transmit data empty or flash
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13. DTC