QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet
QG82945GSE S LB2R
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QG82945GSE S LB2R Summary of contents
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... Mobile Intel® 945 Express Chipset Family Datasheet June 2008 Document Number: 309219-006 ...
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... APPLICATION IN WHICH THE FAILURE OF THE INTEL PRODUCT COULD CREATE A SITUATION WHERE PERSONAL INJURY OR DEATH MAY OCCUR. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them ...
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... Processor Support .................................................................................. 28 1.4.2 System Memory Support ......................................................................... 28 1.4.3 Internal Graphics ................................................................................... 28 1.4.4 DMI...................................................................................................... 28 1.4.5 Package ................................................................................................ 28 1.5 Mobile Intel® 945GSE Express Chipset Feature Support ......................................... 29 1.5.1 Analog TV-Out ....................................................................................... 29 1.6 Mobile Intel® 940GML Express Chipset Feature Support ......................................... 29 1.6.1 Processor Support .................................................................................. 29 1.6.2 System Memory Support ......................................................................... 29 1.6.3 Internal Graphics ................................................................................... 29 1.6.4 ICH Support .......................................................................................... 29 1.6.5 Power Management ................................................................................ 29 1.6.6 ISIPP Support ........................................................................................ 29 1.7 Mobile Intel® 943GML Express Chipset Feature Support ......................................... 30 1 ...
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Host Interface Reference and Compensation...............................................39 2.2 DDR2 DRAM Interface ........................................................................................40 2.2.1 DDR2 SDRAM Channel A Interface ............................................................40 2.2.2 DDR2 SDRAM Channel B Interface ............................................................41 2.2.3 DDR2 Common Signals............................................................................42 2.2.4 DDR2 SDRAM Reference and Compensation ...............................................43 2.3 PCI Express-Based Graphics ...
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VID - Vendor Identification ...................................................................... 81 5.1.2 DID - Device Identification ...................................................................... 81 5.1.3 PCICMD - PCI Command ......................................................................... 81 5.1.4 PCISTS - PCI Status ............................................................................... 83 5.1.5 RID - Revision Identification .................................................................... 84 5.1 Class Code ...
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C0AIT - Channel 0 Adaptive Idle Timer Control ......................................... 137 6.2.20 C0GTEW - Channel 0 (G)MCH Throttling Event Weight ............................... 137 6.2.21 C0GTC - Channel 0 (G)MCH Throttling Control .......................................... 138 6.2.22 C0DTPEW - Channel 0 Dram Rank Throttling ...
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G5SC - Group 5 Strength Control ........................................................... 159 6.2.74 G6SC - Group 6 Strength Control ........................................................... 159 6.2.75 C1DRAMW - Channel 1 DRAM Width ....................................................... 160 6.2.76 G7SC - Group 7 Strength Control ........................................................... 160 6.2.77 G8SC - Group ...
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EXTTSCS - External Thermal Sensor Control and Status ............................. 191 6.4.25 DFT_STRAP1 – DFT Register .................................................................. 192 6.5 Device 0 MCHBAR ACPI Power Management Controls............................................ 193 6.5.1 Power Management Mode Support Options ............................................... 193 6.5.2 C2C3TT - C2 to ...
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VID1 - Vendor Identification .................................................................. 227 7.1.2 DID1 - Device Identification................................................................... 228 7.1.3 PCICMD1 - PCI Command...................................................................... 228 7.1.4 PCISTS1 - PCI Status............................................................................ 230 7.1.5 RID1 - Revision Identification................................................................. 231 7.1.6 CC1 - Class Code ................................................................................. 232 7.1.7 CL1 ...
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ESD - Element Self Description ............................................................... 268 7.2.10 LE1D - Link Entry 1 Description .............................................................. 269 7.2.11 LE1A - Link Entry 1 Address ................................................................... 270 7.2.12 PEGTC - PCI Express-G Timeout Control .................................................. 270 7.2.13 PEGCC - PCI Express-G ...
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MMADR - Memory Mapped Range Address ............................................... 305 8.2.11 SVID2 - Subsystem Vendor Identification ................................................ 306 8.2.12 SID2 - Subsystem Identification ............................................................. 306 8.2.13 ROMADR - Video BIOS ROM Base Address ............................................... 307 8.2.14 CAPPOINT - Capabilities Pointer ............................................................. ...
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... FSB Interrupt Overview ......................................................................... 338 10.1.7 APIC Cluster Mode Support .................................................................... 338 10.2 System Memory Controller ................................................................................ 339 10.2.1 Functional Overview .............................................................................. 339 10.2.2 Functional Overview For Ultra Mobile Intel 10.2.3 Memory Channel Organization Modes ...................................................... 340 10.2.4 DRAM Technologies and Organization ...................................................... 342 10.2.5 DRAM Address Mapping ......................................................................... 344 10.2.6 DRAM Clock Generation ......................................................................... 353 10.2.7 DDR2 On Die Termination ...................................................................... 354 10 ...
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... Ballout and Package Information........................................................................... 417 13.1 Mobile Intel 945GM/GME/PM, 943/940GML and Intel 945GT Express Chipset Ballout Diagram......................................................................................................... 417 13.2 Mobile Intel 945GM/GME/PM, 943/940GML and Intel 945GT Express Chipset Pin List 419 13.3 Mobile Intel 945GMS/GSE Express Chipset Ballout Diagram .................................. 437 13.4 Mobile Intel 945GMS/GSE Express Chipset Pin List ............................................... 439 13 ...
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... Mobile Intel 945GMS/GSE Express Chipset Ballout Diagram (Top) Right Half................... 438 33 Intel 82945GU (G)MCH Ballout – Top View (Upper Left Quadrant; Columns 1–16) ........... 455 34 Intel 82945GU (G)MCH Ballout – Top View (Lower Left Quadrant; Columns 1–16) ........... 456 35 Intel 82945GU (G)MCH Ballout – Top View (Upper Middle Quadrant; Columns 17–33) ..... 457 36 Intel 82945GU (G)MCH Ballout – ...
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... Recommended Programming for Available Trip Points ................................................. 391 45 Host/Graphics Clock Frequency Support for 1.05 V Core Voltage for the Mobile Intel 945GM/GME/GMS/GU/GSE and 940 GML Express Chipsets ......................... 396 46 Host/Graphics Clock Frequency Support at 1.5 V Core Voltage for the Intel 945GT Express Chipset Only............................................................................. 396 47 Absolute Maximum Ratings ...
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... Analog TV-out Signals ............................................................................................. 445 83 SDVO Interface Signals ........................................................................................... 445 84 LVDS Signals ......................................................................................................... 446 85 Display Data Channel Signals ................................................................................... 447 86 PLL Signals ............................................................................................................ 447 87 Reset and Misc. Signals ........................................................................................... 448 88 Reserved Signal ..................................................................................................... 448 89 No Connect Signals................................................................................................. 449 90 Power and Ground Signals ....................................................................................... 450 91 Intel 82945GU (G)MCH Ballout By Signal Name .......................................................... 461 16 Datasheet ...
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... Revision History Revision Number -001 Initial release -002 • Added Information on Mobile Intel® 945GMS and 940GML Express Chipsets. and made some minor edits • Removed support for DFGT and HW VLD • In Chapter 1 — in Section 1.1.2 - included support for 4-GB physical memory @ 667 MHz — ...
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Datasheet ...
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... The Intel® 945GU Express Chipset is designed for use with the Intel Processor A100 and A110 in the Intel ultra mobile platform designs. • The Mobile Intel® 945GSE Express Chipset is designed for use with the Intel® Atom™ Processor N270 in the Netbook Platform 2008 designs. ...
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... Figure 1. Intel® Centrino® Duo Technology with Mobile Intel® 945 Express Chipset Family (G)MCH CRT CRT Discrete Discrete 802.11 802.11 3945 3945 a/b/g a/b/g ABG ABG GbE GbE ExpressCard* ExpressCard* Docking Docking The (G)MCH can also be enabled to support external graphics, using the x16 PCI Express* graphics attach port ...
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... ExpressCard ExpressCard Gbe Gbe Note: The Mobile Intel 945GMS/GSE Express Chipset may have notes in BROWN font throughout this document. This is to point out differences which are relative to these two chipsets only. Datasheet Intel® Core® Duo Intel® Core® Duo ...
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... Figure 3. Ultra Mobile Intel® 945GU Express Chipset Example System Diagram UXGA LFP TV PCI Express* SDVO TPV (Supports 8 USB ports) Definition Audio 22 Processor FSB 400 MHz LVDS TV Out Ultra Mobile ® Intel 82945GU GMCH SDVO DMI USB 2.0 IDE ® Intel ® ...
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... Intel® Core™ Duo processor, Intel® Core™ Duo processor LV (Low Voltage), Intel® Core™ Duo processor ULV (Ultra Low Voltage) • Intel® Core™ Solo processor ULV • Intel® Celeron® M processor (Intel Core processor based), Celeron M processor ULV • 533-MHz and 667-MHz front side bus (FSB) support • ...
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... Support for peer segment destination write traffic (no peer-to-peer read traffic) in Virtual Channel 0 only. • APIC and MSI interrupt messaging support. Will send Intel-defined “End Of Interrupt” broadcast message when initiated by the CPU. • Downstream Lock Cycles (including Split Locks) • ...
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... Panel Power Sequencing support • Integrated PWM interface for LCD backlight inverter control 1.1.4.3 TV-Out • Three integrated 10-bit DACS • MacroVision* support (not supported on Mobile Intel 945GME Express Chipset) • Overscaling • NTSC/PAL • Component, S-Video and Composite Output interfaces • HDTV support — ...
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... Chip-to-chip interface between (G)MCH and ICH • Configurable DMI lanes • DMI lane reversal support • 2 GB/s (1 GB/s each direction) point-to-point interface to Intel 82801GBM • 32-bit downstream address • Direct Media Interface asynchronously coupled to core • Supports two Virtual Channels for traffic class performance differentiation • ...
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... All features supported by the Mobile Intel 945GM/GME Express Chipset shall be supported by the Mobile Intel 945PM Express Chipset unless noted otherwise below. However, the Mobile Intel 945PM Express Chipset does not support Integrated Graphics display. Additional features/differences are also listed here, if applicable. ...
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... All features supported by Mobile Intel 945GM/945GME Express Chipset shall be supported by Intel 945GMS Express Chipset unless noted otherwise below. However, The Mobile Intel 945GMS Express Chipset does not include support for External Graphics via a PCIe Interface. Additional features/differences are also listed here, if applicable ...
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... The Mobile 940GML Express Chipset does not include support for External Graphics via a PCIe interface. 1.6.1 Processor Support • Celeron M processor (Intel Core processor based), Celeron M processor ULV • 533-MHz FSB support only 1.6.2 System Memory Support • Maximum Memory supported per rank) • ...
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... The following sections describe the key differences between the 945GU Express Chipset and the Mobile Intel 945GMS Express Chipset. 1.8.1 Processor Support • Intel® Processor A100 and A110 Process with 512-KB L2 Cache 400-MHz front side bus (FSB) support 1.8.2 System Memory Support • ...
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... Introduction 1.8.7 ICH Support • Support for Intel ICH7-U 1.8.8 DMI • Configurable as x2 DMI lane interface 1.8.9 Package • FCBGA • Ball Count: 1249 balls • Package Size • Ball Pitch: 0.593-mm x 0.893-mm pitch Datasheet 31 ...
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... PCI interface, LPC interface, USB2, ATA-100, and other I/O functions. (ICH7M) It communicates with the (G)MCH over a proprietary interconnect called DMI. Intel® The Digital Home variant of the I/O Controller Hub with support for Intel® 82801GHM Centrino® Duo technology. In addition to the features of the 82801GBM, It (ICH7M) includes support for 2 additional PCIe* ports and Intel® ...
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... TMDS, LVDS, TV-Out). This interface is not electrically compatible with the previous digital display channel - DVO. For the Mobile Intel 945GM/GME and Intel 945GT Express Chipsets, it will be multiplexed on a portion of the x16 graphics PCI Express interface ...
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... Processor Process Datasheet Intel® Core™ Duo Processor and Intel® Core™ Solo Processor Process Specification Update Intel® I/O Controller Hub 7 (ICH7) Family Datasheet Intel® I/O Controller Hub 7 (ICH7) Family Specification Update PCI Local Bus Specification 2.3 PCI Express* Base Specification 1.1 PCI Power Management Interface Specification 1 ...
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Signal Description 2 Signal Description This section describes the (G)MCH signals. These signals are arranged in functional groups according to their associated interface. The following notations are used to describe the signal type: Notations I Input pin O Output pin ...
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Host Interface Unless otherwise noted, the voltage level for all signals in this interface is tied to the termination voltage of the host bus (V 2.1.1 Host Interface Signals Signal Name HADS# HBNR# HBPRI# HBREQ0# HCPURST# HDBSY# HDEFER# 36 ...
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Signal Description Signal Name HDINV[3:0]# HDRDY# HA[31:3]# HADSTB[1:0]# HD[63:0]# HDSTBP[3:0]# HDSTBN[3:0]# HHIT# Datasheet Type Host Dynamic Bus Inversion: Driven along with the HD[63:0]# signals. Indicates if the associated signals are inverted or not. HDINV[3:0]# are asserted such that the number ...
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Signal Name HHITM# HLOCK# HREQ[4:0]# HTRDY# HRS[2:0]# HDPWR# HCPUSLP# 38 Type Host Hit Modified: Indicates that a caching agent holds a modified version of the I/O requested line and that this agent assumes responsibility for AGTL+ providing the line. Also, ...
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Signal Description Signal Name THERMTRIP# 2.1.2 Host Interface Reference and Compensation Signal Name HVREF HXRCOMP HXSCOMP HXSWING HYRCOMP HYSCOMP HYSWING Datasheet Type Connects between the processor and the ICH7-M. Assertion of THERMTRIP# (Thermal Trip) indicates the (G)MCH junction temperature has ...
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DDR2 DRAM Interface 2.2.1 DDR2 SDRAM Channel A Interface Signal Name SA_DQ[63:0] SA_DM[7:0] SA_DQS[7:0] SA_DQS[7:0]# SA_MA[13:0] SA_BS[2:0] SA_RAS# SA_CAS# SA_WE# SA_RCVENIN# SA_RCVENOUT# 40 Type I/O Data Bus: SSTL1.8 DDR2 Channel A data signal interface to the SDRAM data bus. ...
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... Signal Description 2.2.2 DDR2 SDRAM Channel B Interface Note: The Ultra Mobile Intel 945GU Express Chipset does not support Channel B. These signals are Not on the Ultra Mobile Intel 945GU Express Chipset. Signal Name SB_DQ[63:0] SB_DM[7:0] SB_DQS[7:0] SB_DQS[7:0]# SB_MA[13:0] SB_BS[2:0] SB_RAS# SB_CAS# Datasheet (Sheet ...
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... Express Chipset. Clock Output: Used to emulate source-synch clocking for reads. O Leave as No Connect. SSTL1.8 Note: These signals do not exist on the Mobile Intel 945GMS/GSE Express Chipset. Type SDRAM Differential Clock: (2 per DIMM) These are the SDRAM Differential Clock signals O The crossing of the positive edge of SM_CKx and the SSTL1 ...
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Signal Description Signal Name SM_CKE[3:0] SM_ODT[3:0] 2.2.4 DDR2 SDRAM Reference and Compensation Signal Name SM_RCOMPN SM_RCOMPP SM_VREF[1:0] SM_OCDCOMP[1:0] Datasheet Type Clock Enable: (1 per rank) SM_CKE[3:0] is used: to initialize the SDRAMs during power-up, to power-down SDRAM ranks, to place ...
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... Express Chipset. PCI Express* Note: Only EXP_A_RXN[5, 0] and EXP_A_RXP[5, 0] are on the Ultra Mobile 945GU Express Chipset. PCI Express Graphics Transmit Differential Pair Note: These signals do not exist on the Mobile Intel O 945GMS/GSE Express Chipset. PCI Express Note: Only EXP_A_TXN[5, 0] and EXP_A_TXP[5, 0] are on the Ultra Mobile 945GU Express Chipset ...
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... SDVOC_INT# SDVOC_INT NOTE: 1. The Mobile Intel 945GMS/GSE Express Chipset employs only the SDVO B port and associated signals (TVCLKIN, INT and FLDSTALL differential pairs) as highlighted above. 2. The SDVO to PCIe signal mapping shown in the table above is applicable for the non- reversed SDVO-only mode. For more details on SDVO mapping for all possible ...
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... Mobile Intel 945GU Express Chipset. 2.5 Integrated Graphics Interface Signals 2.5.1 CRT DAC SIGNALS Note: The Ultra Mobile Intel 945GU Express Chipset does not support a CRT interface. Theses signals are Not on the Ultra Mobile Intel 945GU Express Chipset. Signal Name CRT_RED CRT_RED# CRT_GREEN ...
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... A S-Video: Chrominance analog signal Component: Chrominance (Pr) analog signal TV D-connector Select: O Supports 525i, 525p, 750p, 1125i and 1125p A Note: This signal is Not on the Ultra Mobile Intel 945GU Express Chipset. O Current Return for TVDAC Channel A: A Connect to ground on board O Current Return for TVDAC Channel B: ...
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... LVDS Signals Signal Name LADATAP[2:0] LADATAN[2:0] LA_CLKP LA_CLKN LDVS Channel B (Not on the Intel® 945GU Express Chipset) LBDATAP[2:0] LBDATAN[2:0] LB_CLKP LB_CLKN LVDD_EN HVCMOS LBKLT_EN HVCMOS LBKLT_CTL HVCMOS LIBG LVREFH LVREFL LVBG 48 Type LDVS Channel A O Channel A differential data output – positive ...
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Signal Description 2.5.4 Serial DVO Interface All of the pins in this section are multiplexed with the upper eight lanes of the PCI Express interface. Note: On the Ultra Mobile 945GU Express Chipset the SDVO signals are Not multiplexed. Note: ...
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... Signal Name SDVOC_CLKN SDVO_TVCLKIN SDVO_TVCLKIN# SDVO_FLDSTALL SDVO_FLDSTALL# SDVOB_INT SDVOB_INT# SDVOC_INT SDVOC_INT# Note: The Mobile Intel 945GMS/GSE Express Chipset supports only the signals marked in Brown. 2.5.5 Display Data Channel (DDC) and GMBUS Support Signal Name LCTLA_CLK LCTLB_DATA DDCCLK DDCDATA LDDC_CLK 50 Type O Serial Digital Video C Clock Complement ...
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... External Clock Request: (G)MCH drives CLK_REQ# to control the PCI Express* O differential clock input to itself. COD Not supported with the Intel® 915 Express Chipset family clocking solutions. Differential Host Clock In: I Differential clock input for the host PLL. This is a low voltage Diff Clk differential signal and runs at the FSB data rate ...
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... H_BSEL [2:0] (CFG[2:0]) CFG[17:3] CFG[20:18] PM_PM_BM_BUSY# PM_EXTTS[1:0]# ICH_SYNC# Note: Some of the strappings mentioned in the table above do not exist on the Mobile Intel 945GMS/GSE Express Chipset. For more details, please refer to strapping definitions. 52 Type Reset In: When asserted this signal will asynchronously reset the I (G)MCH logic. This signal is connected to the PLTRST# output of the ICH7M ...
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... Platform Power Planes Interface (G)MCH Core DDR 2 FSB Buffers CRT DAC Note: This signal Power Plane is Not on the Ultra Mobile Intel 945GU Express Chipset. TV DAC LVDS Transmitter/Analog LVDS Digital PCI Express PCI Express Bandgap V HPLL/DPLL/PCIEPLL GPIO 2.9 Power and Ground ...
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... Characteristic Thermal Expansion (CTE) mismatch of the Die to package interface expected that in some cases, these balls may crack partially or completely, however, this will have no impact to our product performance or reliability. Intel has added these balls primarily to serve as sacrificial stress absorbers. V NTCF Core V (1 ...
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Signal Description 2.10 Reset States and Pull-up / Pull-downs This section describes the expected states of the (G)MCH I/O buffers during and immediately after the assertion of RSTIN#. This table only refers to the contributions on the interface from the ...
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Signal Name HD[1]# HD[0]# HDSTBP[3:0]# HDSTBN[3:0]# HHIT# HHITM# HLOCK# HREQ[4:0]# HTRDY# HRS[2:0]# HDPWR# HCPUSLP# THERMTRIP# 2.10.2 Host Interface Reference and Compensation Signal Name HVREF HXRCOMP HXSCOMP HXSWING HYRCOMP HYSCOMP HYSWING 56 (Sheet State during State after Type ...
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Signal Description 2.10.3 DDR2 SDRAM Channel A Interface Signal Name SA_DQ[63:0] SA_DM[7:0] SA_DQS[7:0] SA_DQS[7:0]# SA_MA[13:0] SA_BS[2:0] SA_RAS# SA_CAS# SA_WE# SA_RCVENIN# SA_RCVENOUT# Datasheet State during State after Type RSTIN# Assertion Deassertion I/O TRI SSTL1.8 O TRI SSTL1.8 I/O TRI SSTL1.8 I/O ...
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DDR2 SDRAM Channel B Interface Signal Name SB_DQ[63:0] SB_DM[7:0] SB_DQS[7:0] SB_DQS[7:0]# SB_MA[13:0] SB_BS[2:0] SB_RAS# SB_CAS# SB_WE# SB_RCVENIN# SB_RCVENOUT# 2.10.5 DDR2 Common Signals Signal Name SM_CK[1:0], SM_CK[3:2] SM_CK[1:0]#, SM_CK[3:2]# SM_CS[3:0]# SM_CKE[3:0] SM_ODT[3:0] 58 State during State after Type RSTIN# Assertion ...
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Signal Description 2.10.6 DDR SDRAM Reference and Compensation Signal Name SMRCOMPN SMRCOMPP SMVREF[1:0] 2.10.7 PCI Express-Based Graphics Interface Signals (PCIe x16 Mode) Signal Name EXP_RXN[15:0] EXP_RXP[15:0] EXP_TXN[15:0] EXP_TXP[15:0] EXP_COMPO EXP_COMPI Datasheet State during Type RSTIN# Assertion I I/O ...
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PCI Express-Based Graphics Interface Signals (SDVO Mode) Signal Name SDVOC_RED SDVOC_RED# SDVOC_GREEN SDVOC_GREEN# SDVOC_BLUE SDVOC_BLUE# SDVOC_CLKP SDVOC_CLKN SDVOC_INT SDVOC_INT# SDVOB_CLKP SDVOB_CLKN SDVOB_RED SDVOB_RED# SDVOB_GREEN SDVOB_GREEN# SDVOB_BLUE SDVOB_BLUE# 60 (Sheet State during Type RSTIN# Assertion SDVO C ...
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Signal Description Signal Name SDVOB_INT SDVOB_INT# SDVO_TVCLKIN SDVO_TVCLKIN# SDVO_FLDSTALL SDVO_FLDSTALL# 2.10.9 DMI Signal Name DMI_RXN[3:0] DMI_RXP[3:0] DMI_TXN[3:0] DMI_TXP[3:0] Datasheet (Sheet State during Type RSTIN# Assertion I TRI PCI Express I TRI PCI Express SDVO Common Signals I ...
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CRT DAC SIGNALS Signal Name CRT_RED CRT_RED# CRT_GREEN CRT_GREEN# CRT_BLUE CRT_BLUE# CRT_IREF CRT_HSYNC CRT_VSYNC 2.10.11 Analog TV-out Signals Signal Name TVDAC_A TVDAC_B TVDAC_C TV_IRTNA TV_IRTNB TV_IRTNC TV_IREF 62 State during State after Type RSTIN# Assertion Deassertion O TRI A ...
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Signal Description 2.10.12 LVDS Signals Signal Name LADATAP[2:0] LADATAN[2:0] LACLKP LACLKN LBDATAP[2:0] LBDATAN[2:0] LBCLKP LBCLKN LVDD_EN LBKLT_EN LBKLT_CRTL LVREFH LVREFL LIBG Datasheet State during Type RSTIN# Assertion Deassertion LDVS Channel A O DRIVE 0 LVDS O DRIVE 0 LVDS O ...
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Display Data Channel (DDC) and GMBUS Support Signal Name LCTLA_CLK LCTLB_DATA CRT_DDCCLK CRT_DDCDATA LDDC_CLK LDDC_DATA SDVOCTRL_CLK SDVOCTRL_DATA 2.10.14 PLL Signals Signal Name HCLKP HCLKN GCLKP GCLKN DREF_CLKP DREF_CLKN DREF_SSCLKP DREF_SSCLKN 64 State during State after Type RSTIN# Assertion Deassertion ...
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Signal Description 2.10.15 Reset and Miscellaneous Signals Signal Name RSTIN# PWROK H_BSEL [2:0] (CFG[2:0]) CFG[17:3] EXT_TS[1:0]# ICH_SYNC# Datasheet State during Type RSTIN# Assertion Deassertion I DRIVE 0 HVCMOS I DRIVE 0 HVCMOS I PD HVCMOS I PD AGTL ...
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Signal Description Datasheet ...
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Register Description 3 (G)MCH Register Description 3.1 Register Terminology The following table shows the register-related terminology used in this datasheet. For general terminology, refer to the Abbreviation Read Only bit(s). Writes to these bits have no effect. This may ...
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Abbreviation Read / Write / Sticky bit(s). These bits can be read and written by software. Bits are not cleared by “warm” reset, but will be reset with a cold/ R/W/S complete reset (for PCI Express related bits a cold ...
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... ICH logically constitute PCI Bus 0 to configuration software. This is shown in the following figure. . Figure 4. Conceptual Mobile Intel 945GM/GME/PM/GMS/GU/GSE, 943/940GML and Intel 945GT Express Chipset Platform PCI Configuration Diagram Datasheet CPU PCI Configuration Window in I/O Space Host-PCI Express Bridge ...
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The (G)MCH contains four PCI devices within a single physical component. The configuration registers for the four devices are mapped as devices residing on PCI Bus 0. Device 0: Host Bridge/DRAM Controller. Logically this appears as a PCI device residing ...
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Configuration Process and Registers 4.2.2 Logical PCI Bus 0 Configuration Mechanism The (G)MCH decodes the Bus Number (bits 23:16) and the Device Number fields of the CONFIG_ADDRESS register. If the Bus Number field of CONFIG_ADDRESS is 0 the configuration ...
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Figure 6. DMI Type 1 Configuration Address Translation Re served DMI TYPE 1 CONFIGURATION ADDRESS EXTENSION Reserved 4.2.4 PCI Express Enhanced Configuration ...
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Configuration Process and Registers Figure 7. Memory Map to PCI Express Device Configuration Space 0xFFFFFFF 0x1FFFFF 0xFFFFF 0 Located by PCI Express Base Address As with PCI devices, each device is selected based on decoded address information that is ...
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Configuration Cycle Flowchart Figure 8. (G)MCH Configuration Cycle Flowchart GMCH Generates Type 1 Access to PCI Express Device GMCH Generates Master Abort 74 (G)MCH Configuration Process and Registers DW I/O Write to CONFIG_ADDRESS with bit ...
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... Writes to Reserved registers have no effect on the (G)MCH. Registers that are marked as Intel Reserved must not be modified by system software. Writes to Intel Reserved registers may cause system failure. Reads from Intel Reserved registers may return a non-zero value. ...
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CONFIG_ADDRESS—Configuration Address Register I/O Address: Size: CONFIG_ADDRESS is a 32-bit register that can be accessed only as a DW. A byte or word reference will “pass through” the Configuration Address register and DMI onto the PCI_A bus as an ...
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Configuration Process and Registers Access & Bit Default R/W 10:8 000b R/W 7:2 00h RO 1:0 00b 4.4.2 CONFIG_DATA—Configuration Data Register I/O Address: Size: CONFIG_DATA is a 32-bit read/write window into configuration space. The portion of configuration space that ...
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Configuration Process and Registers Datasheet ...
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Host Bridge Device 0 - Configuration Registers (D0:F0) 5 Host Bridge Device 0 - Configuration Registers (D0:F0) Warning: Address locations that are not listed are considered Reserved registers locations. Reads to Reserved registers may return non-zero values. Writes to reserved ...
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... Error Command Reserved Scratchpad Data Capability Identifier Reserved NOTES: 1. Valid for all Mobile Intel 945 Express Chipsets except for the Mobile Intel 945GME/GSE Express Chipset. 2. Valid for the Mobile Intel 945GME/GSE Express Chipset only. 80 Host Bridge Device 0 - Configuration Registers (D0:F0) Register Register ...
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... This register combined with the Vendor Identification register uniquely identifies any PCI device. Bit Access 15:0 RO NOTES: 1. Valid for all Mobile Intel 945 Express Chipsets except for the Mobile Intel 945GME/GSE Express Chipset. 2. Valid for the Mobile Intel 945GME/GSE Express Chipset only. 5.1.3 PCICMD - PCI Command B/D/F/Type: Address Offset: ...
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Bit Access 15:10 RO 9:9 RO 8:8 R/W 7:7 RO 6:6 RO 5:5 RO 4:4 RO 3:3 RO 2:2 RO 1 Host Bridge Device 0 - Configuration Registers (D0:F0) Default Value 00h Reserved Fast Back-to-Back Enable ...
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Host Bridge Device 0 - Configuration Registers (D0:F0) 5.1.4 PCISTS - PCI Status B/D/F/Type: Address Offset: Default Value: Access: Size: This status register reports the occurrence of error events on Device 0’s PCI interface. Since MCH Device 0 does not ...
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Bit Access 6:5 RO 4:4 RO 3:0 RO 5.1.5 RID - Revision Identification B/D/F/Type: Address Offset: Default Value: Access: Size: This register contains the revision number of the (G)MCH Device 0. Bit Access 7 Host Bridge Device 0 ...
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Host Bridge Device 0 - Configuration Registers (D0:F0) 5.1 Class Code B/D/F/Type: Address Offset: Default Value: Access: Size: This register identifies the basic function of the device, a more specific sub-class, and a register-specific programming interface. Bit Access ...
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HDR - Header Type B/D/F/Type: Address Offset: Default Value: Access: Size: This register identifies the header layout of the configuration space. No physical register exists at this location. Bit Access 7:0 RO 5.1.9 SVID - Subsystem Vendor Identification B/D/F/Type: ...
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Host Bridge Device 0 - Configuration Registers (D0:F0) 5.1.10 PAGE BREAKSID - Subsystem Identification B/D/F/Type: Address Offset: Default Value: Access: Size: This value is used to identify a particular subsystem. Bit Access 15:0 R/WO 5.1.11 CAPPTR - Capabilities Pointer B/D/F/Type: ...
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EPBAR - Egress Port Base Address B/D/F/Type: Address Offset: Default Value: Access: Size: This is the base address for the Egress Port Root Complex MMIO configuration space. This window of addresses contains the Egress Port Root Complex register set ...
Page 89
Host Bridge Device 0 - Configuration Registers (D0:F0) 5.1.13 MCHBAR - (G)MCH Memory Mapped Register Range Base B/D/F/Type: Address Offset: Default Value: Access: Size: This is the base address for the MCH MMIO Configuration space. There is no physical memory ...
Page 90
... The PCI Express Base Address [bits 15:12] must never be set to 0Fh because this would result in PCI Express configuration space overlapping the HSEG space required for the Intel® Pentium® 4 processor to respond to interrupts and system management events. The PCI Express Base Address cannot be below the address written to the top of low usable dram register (TOLUD) ...
Page 91
Host Bridge Device 0 - Configuration Registers (D0:F0) Bit Access 27 R/W/L 26 R/W/L 25:3 RO 2:1 R/W/L 0 R/W/L Datasheet (Sheet Default Value 128-MB Address Mask: This bit is either part of the PCI Express Base ...
Page 92
DMIBAR - MCH-ICH Serial Interconnect Ingress Root Complex B/D/F/Type: Address Offset: Default Value: Access: Size: This is the base address for the DMI Root Complex MMIO configuration space. This window of addresses contains the DMI Root Complex register set ...
Page 93
Host Bridge Device 0 - Configuration Registers (D0:F0) 5.1.16 GGC - (G)MCH Graphics Control (Device 0) B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access 15:7 RO 6:4 R/W/L 3 R/W Datasheet 0/0/0/PCI 52-53h 0030h R/W/L; ...
Page 94
DEVEN - Device Enable B/D/F/Type: Address Offset: Default Value: Access: Size: This register allows for enabling/disabling of PCI devices and functions that are within the MCH. This table describes the behavior of all combinations of transactions to devices controlled ...
Page 95
Host Bridge Device 0 - Configuration Registers (D0:F0) 5.1.18 PAM0 - Programmable Attribute Map 0 B/D/F/Type: Address Offset: Default Value: Access: Size: This register controls the read, write, and shadowing attributes of the BIOS area from 0F0000h-0FFFFFh. The MCH allows ...
Page 96
Bit Access 7:6 RO 5:4 R/W/L 3:0 RO 5.1.19 PAM1 - Programmable Attribute Map 1 B/D/F/Type: Address Offset: Default Value: Access: Size: This register controls the read, write, and shadowing attributes of the BIOS areas from 0C0000h-0C7FFFh. Bit Access 7:6 ...
Page 97
Host Bridge Device 0 - Configuration Registers (D0:F0) Bit Access 1:0 R/W/L 5.1.20 PAM2 - Programmable Attribute Map 2 B/D/F/Type: Address Offset: Default Value: Access: Size: This register controls the read, write, and shadowing attributes of the BIOS areas from ...
Page 98
PAM3 - Programmable Attribute Map 3 B/D/F/Type: Address Offset: Default Value: Access: Size: This register controls the read, write, and shadowing attributes of the BIOS areas from 0D0000h-0D7FFFh. Bit Access 7:6 RO 5:4 R/W/L 3:2 RO 1:0 R/W/L 98 ...
Page 99
Host Bridge Device 0 - Configuration Registers (D0:F0) 5.1.22 PAM4 - Programmable Attribute Map 4 B/D/F/Type: Address Offset: Default Value: Access: Size: This register controls the read, write, and shadowing attributes of the BIOS areas from 0D8000h-0DFFFFh. Bit Access 7:6 ...
Page 100
PAM5 - Programmable Attribute Map 5 B/D/F/Type: Address Offset: Default Value: Access: Size: This register controls the read, write, and shadowing attributes of the BIOS areas from 0E0000h-0E7FFFh. Bit Access 7:6 RO 5:4 R/W/L 3:2 RO 1:0 R/W/L 100 ...
Page 101
Host Bridge Device 0 - Configuration Registers (D0:F0) 5.1.24 PAM6 - Programmable Attribute Map 6 B/D/F/Type: Address Offset: Default Value: Access: Size: This register controls the read, write, and shadowing attributes of the BIOS areas from 0E8000h-0EFFFFh. Bit Access 7:6 ...
Page 102
LAC - Legacy Access Control B/D/F/Type: Address Offset: Default Value: Access: Size: This 8-bit register controls a fixed DRAM hole from 15-16 MB. Bit Access 7 R/W/L 6 R/W 102 Host Bridge Device 0 - Configuration Registers ...
Page 103
Host Bridge Device 0 - Configuration Registers (D0:F0) 5.1.26 TOLUD - Top of Low Used DRAM Register B/D/F/Type: Address Offset: Default Value: Access: Size: This 8-bit register defines the Top of Usable Dram. Graphics Stolen Memory and TSEG are within ...
Page 104
SMRAM - System Management RAM Control B/D/F/Type: Address Offset: Default Value: Access: Size: The SMRAMC register controls how accesses to Compatible and Extended SMRAM spaces are treated. The Open, Close, and Lock bits function only when G_SMRAME bit is ...
Page 105
Host Bridge Device 0 - Configuration Registers (D0:F0) Bit Access 2:0 RO 5.1.28 ESMRAMC - Extended System Management RAM Control B/D/F/Type: Address Offset: Default Value: Access: Size: The Extended SMRAM register controls the configuration of Extended SMRAM space. The Extended ...
Page 106
Bit Access 3 RO 2:1 R/W/L 0 R/W/L 5.1.29 TOM - Top Of Memory B/D/F/Type: Address Offset: Default Value: Access: Size: 106 Host Bridge Device 0 - Configuration Registers (D0:F0) (Sheet Default Value L2 Cache Enable for ...
Page 107
Host Bridge Device 0 - Configuration Registers (D0:F0) 5.1.30 ERRSTS - Error Status B/D/F/Type: Address Offset: Default Value: Access: Size: This register is used to report various error conditions via the SERR messaging mechanism. An SERR message is generated on ...
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ERRCMD - Error Command B/D/F/Type: Address Offset: Default Value: Access: Size: This register controls the MCH responses to various system errors. Since the MCH does not have an SERRB signal, SERR messages are passed from the MCH to the ...
Page 109
... Mobile Intel® 945PM Express Chipset 101: Intel® 945GT Express Chipset Others: Reserved Reserved Integrated TVout Capable: 0: (G)MCH capable of Integrated TV out. (Mobile Intel 945GM/ GME/GMS/GU/GSE, 943/940GML and Intel 945GT Express 0b Chipset) 1: (G)MCH not capable of Integrated TV out. (Mobile Intel ...
Page 110
... MHz but SW must program the render frequency to supported values, i.e., 133 MHz 0b Reserved Serial Digital Video Out Capable: 0: (G)MCH capable of serial digital video output. (Mobile Intel 945GM/GME/GMS/GU/GSE, 943/940GML and Intel 945GT 0b Express Chipset) 1: (G)MCH not capable of serial digital video output. (Mobile ...
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Host Bridge Device 0 - Configuration Registers (D0:F0) Bit Access 34:32 RO 31: 27:24 RO 23:16 RO 15:8 RO 7:0 RO Datasheet Default Description Value DDR2 Frequency Capability: 010:(G)MCH capable DDR2-667 011:(G)MCH capable of ...
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Host Bridge Device 0 - Configuration Registers (D0:F0) Datasheet ...
Page 113
Device 0 Memory Mapped I/O Register 6 Device 0 Memory Mapped I/O Register Note: All accesses to the memory mapped registers must be made as a single dword (4 bytes) or less. Access must be aligned on a natural boundary. ...
Page 114
Table 4. Device 0 MCHBAR Chipset Control Registers (Sheet Register Name Channel 0 DRAM Bank Architecture Channel 0 DRAM Timing Register 0 Channel 0 DRAM Timing Register 1 Channel 0 DRAM Timing Register 2 Reserved Channel 0 ...
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Device 0 Memory Mapped I/O Register Table 4. Device 0 MCHBAR Chipset Control Registers (Sheet Register Name Channel 1 DRAM Timing Register 1 Channel 1 DRAM Timing Register 2 Reserved Channel 1 DRAM Controller Mode 0 Channel ...
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Table 4. Device 0 MCHBAR Chipset Control Registers (Sheet Register Name Reserved DQS Master Timing Reserved RCVENOUTB Master Timing Reserved Channel 0 WL0 RCVENOUT Slave Timing Channel 0 WL1 RCVENOUT Slave Timing Channel 0 WL2 RCVENOUT Slave ...
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Device 0 Memory Mapped I/O Register Table 4. Device 0 MCHBAR Chipset Control Registers (Sheet Register Name Global/System Memory RCOMP Control Reserved Channel 0 DRAM Width Reserved Group 1 Strength Control Reserved Group 2 Strength Control Reserved ...
Page 118
Table 4. Device 0 MCHBAR Chipset Control Registers (Sheet Register Name Group 5 Slew Rate Pull-down Table Group 6 Slew Rate Pull-up Table Group 6 Slew Rate Pull-down Table Group 7 Slew Rate Pull-up Table Group 7 ...
Page 119
Device 0 Memory Mapped I/O Register 6.2.5 C0DRB0 - Channel 0 DRAM Rank Boundary 0 B/D/F/Type: Address Offset: Default Value: Access: Size: The DRAM rank boundary register defines the upper boundary address of each DRAM rank with a granularity of ...
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C0DRB2 - Channel 0 DRAM Rank Boundary 1 B/D/F/Type: Address Offset: Default Value: Access: Size: The operation of this register is detailed in the description for register C0DRB0. 6.2.8 C0DRB3 - Channel 0 DRAM Rank Boundary 1 B/D/F/Type: Address ...
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Device 0 Memory Mapped I/O Register 6.2.9 C0DRA0 - Channel 0 DRAM Rank 0,1 Attribute B/D/F/Type: Address Offset: Default Value: Access: Size: The DRAM rank attribute registers define the page sizes to be used when accessing different ranks. These registers ...
Page 122
C0DRA2 - Channel 0 DRAM Rank 2,3 Attribute B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access 7:7 RO 6:4 R/W 3:3 RO 2:0 R/W 6.2.11 C0DCLKDIS - Channel 0 DRAM Clock Disable B/D/F/Type: Address Offset: Default Value: Access: ...
Page 123
Device 0 Memory Mapped I/O Register Channel Rank Clocks Bit Access 7 R/W 2 R/W 1 R/W 0 R/W 6.2.12 C0BNKARC - Channel 0 DRAM Bank Architecture B/D/F/Type: Address Offset: ...
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Bit Access 5:4 R/W 3:2 R/W 1:0 R/W 6.2.13 C0DRT0 - Channel 0 DRAM Timing Register 0 B/D/F/Type: Address Offset: Default Value: Access: Size: This 32-bit register defines the timing parameters for all devices in this channel. The BIOS programs ...
Page 125
Device 0 Memory Mapped I/O Register Bit Access 31:28 R/W 27:24 R/W Datasheet (Sheet Default Value Back-to-Back Write to Precharge Command Spacing (Same Bank): This field determines the number of clocks between write command and a subsequent ...
Page 126
Bit Access 23:22 R/W 126 (Sheet Default Value Back-to-Back Write-Read Command Spacing (Different Rank): This field determines the number of turnaround clocks on the data bus that needs to be inserted between write command and a subsequent ...
Page 127
Device 0 Memory Mapped I/O Register Bit Access 21:20 R/W 19:18 R/W 17:17 RO Datasheet (Sheet Default Value Back-to-Back Read-Write Command Spacing: This field determines the number of turnaround clocks between the read command and a subsequent ...
Page 128
Bit Access 16:16 R/W 15:11 R/W 10:9 RO 8:4 R/W 3:0 R/W 128 (Sheet Default Value Back-to-Back Read Command Spacing (Different Rank): This field controls the turnaround time on the DQ bus for Rd-RD sequence to different ...
Page 129
Device 0 Memory Mapped I/O Register 6.2.14 C0DRT1 - Channel 0 DRAM Timing Register 1 B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access 31:30 R/W 29:28 R/W 27:24 R/W 23:19 R R/W Datasheet 0/0/0/MCHBAR ...
Page 130
... DDR2 667 MHz (Validated for DDR2 533 MHz (Validated for DDR2 400 MHz Note: The timings validated by Intel for each DDR2 frequency are indicated above. 0b Reserved Device 0 Memory Mapped I/O Register Description 256 Mb 512 ...
Page 131
... DRAM Clocks (Validated for DDR2 667 MHz) 100 6 DRAM Clocks 101-111 Reserved Note: The timings validated by Intel for each DDR2 frequency are indicated above. 0b Reserved DRAM RASB Precharge (tRP): This bit controls the number of clocks that are inserted between a row precharge command and an activate command to the same rank ...
Page 132
C0DRT2 - Channel 0 DRAM Timing Register 2 B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access 31:30 R/W 29:18 RO 17:16 R/W 15:11 RO 10:8 R/W 7:0 R/W 6.2.16 C0DRC0 - Channel 0 DRAM Controller Mode 0 B/D/F/Type: ...
Page 133
Device 0 Memory Mapped I/O Register Bit Access 23:16 R/W 15 R/W 14 R/W 13:12 R 10:8 R Datasheet (Sheet Default Value 000h Reserved CMD Pin Dual Copy Enable Single-channel mode, ...
Page 134
Bit Access 6:4 R/W 134 (Sheet Default Value Mode Select (SMS): These bits select the special operational mode of the DRAM interface. The special modes are intended for initialization at power up. 000: Post Reset state – ...
Page 135
Device 0 Memory Mapped I/O Register Bit Access R/W 1:0 RO 6.2.17 C0DRC1 - Channel 0 DRAM Controller Mode 1 B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access 31:20 R/W 19:16 R/W 15:13 R/W 12 R/W ...
Page 136
Bit Access 10:9 R/W 8 R/W 7:0 R/W 6.2.18 C0DRC2 - Channel 0 DRAM Controller Mode 2 B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access 31:28 RO 27:24 R/W 23: R/W 11:9 RO 8:2 R/W 1:0 RO ...
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Device 0 Memory Mapped I/O Register 6.2.19 C0AIT - Channel 0 Adaptive Idle Timer Control B/D/F/Type: Address Offset: Default Value: Access: Size: This register controls Characteristics of Adaptive Idle Timer Mechanism. 6.2.20 C0GTEW - Channel 0 (G)MCH Throttling Event Weight ...
Page 138
C0GTC - Channel 0 (G)MCH Throttling Control B/D/F/Type: Address Offset: Default Value: Access: Size: This register contains programmable Event weights that are input into the averaging filter. Each Event weight is a normalized 8-bit value that the BIOS must ...
Page 139
Device 0 Memory Mapped I/O Register 6.2.22 C0DTPEW - Channel 0 Dram Rank Throttling Passive Event Weights B/D/F/Type: Address Offset: Default Value: Access: Size: This register contains programmable Event weights that are input into the averaging filter. Each Event weight ...
Page 140
C0DTAEW - Channel 0 Dram Rank Throttling Active Event Weights B/D/F/Type: Address Offset: Default Value: Access: Size: This register contains programmable Event weights that are input into the averaging filter. Each Event weight is a normalized 8-bit value that ...
Page 141
Device 0 Memory Mapped I/O Register Bit Access 31 R R/W/L 28:25 RO 24:22 R/W/L 21 R/W/L 20 R/W 18:16 R/W/L 15:8 R/W/L 7:0 R/W/L 6.2.25 C0DMC - Channel 0 DRAM Maintenance Control B/D/F/Type: Address ...
Page 142
C0ODT - Channel 0 ODT Control B/D/F/Type: Address Offset: Default Value: Access: Size: The register fields allow control of DRAM and MCH ODT. 6.2.27 C1DRB0 - Channel 1 DRAM Rank Boundary Address 0 B/D/F/Type: Address Offset: Default Value: Access: ...
Page 143
Device 0 Memory Mapped I/O Register 6.2.31 C1BNKARC - Channel 1 DRAM Bank Architecture B/D/F/Type: Address Offset: Default Value: Access: Size: The operation of this register is detailed in the description for register C0BNKARC. 6.2.32 C1DRT0 - Channel 1 DRAM ...
Page 144
C1DRC1 - Channel 1 DRAM Controller Mode 1 B/D/F/Type: Address Offset: Default Value: Access: Size: The operation of this register is detailed in the description for register C0DRC1. 6.2.37 C1DRC2 - Channel 1 DRAM Controller Mode 2 B/D/F/Type: Address ...
Page 145
Device 0 Memory Mapped I/O Register 6.2.39 C1GTEW - Channel 1 (G)MCH Throttling Event Weights B/D/F/Type: Address Offset: Default Value: Access: Size: This register contains programmable Event weights that are input into the averaging filter. Each Event weight is a ...
Page 146
C1GTC - Channel 1 (G)MCH Throttling Control B/D/F/Type: Address Offset: Default Value: Access: Size: This register contains programmable Event weights that are input into the averaging filter. Each Event weight is a normalized 8-bit value that the BIOS must ...
Page 147
Device 0 Memory Mapped I/O Register 6.2.41 C1DTPEW - Channel 1 DRAM Rank Throttling Passive Event Weights B/D/F/Type: Address Offset: Default Value: Access: Size: This register contains programmable Event weights that are input into the averaging filter. Each Event weight ...
Page 148
C1DTAEW - Channel 1 DRAM Rank Throttling Active Event Weights B/D/F/Type: Address Offset: Default Value: Access: Size: This register contains programmable Event weights that are input into the averaging filter. Each Event weight is a normalized 8-bit value that ...
Page 149
Device 0 Memory Mapped I/O Register 6.2.43 C1DTO - Channel 1 Throttling Observation B/D/F/Type: Address Offset: Default Value: Access: Size: This register enables observation of the state of the throttling mechanism and current measured bandwidth information. Bit Access 31:20 RO ...
Page 150
DCC - DRAM Channel Control B/D/F/Type: Address Offset: Default Value: Access: Size: This register controls how the DRAM channels work together. It affects how the CxDRB registers are interpreted and allows them to steer transactions to the correct channel. ...
Page 151
Device 0 Memory Mapped I/O Register Bit Access 8:3 RO 2:2 R/W 1:0 R/W 6.2.47 WCC - Write Cache Control B/D/F/Type: Address Offset: Default Value: Access: Size: 6.2.48 MMARB0 - Main Memory Arbiter Control_0 B/D/F/Type: Address Offset: Default Value: BIOS ...
Page 152
ODTC - On Die Termination Control B/D/F/Type: Address Offset: Default Value: Access: Size: 6.2.52 SMVREFC - System Memory VREF Control B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access 7 R/W/L 6 R/W/L 5:4 RO 3:0 R/W/L 6.2.53 DQSMT ...
Page 153
Device 0 Memory Mapped I/O Register 6.2.55 C0WL0REOST - Channel 0 WL0 RCVENOUT Slave Timing B/D/F/Type: Address Offset: Default Value: Access: Size: This register can be locked by the Global RCOMP Lock bit (GBRCOMPCTL[31]). 6.2.56 C0WL1REOST - Channel 0 WL1 ...
Page 154
WDLLBYPMODE - Write DLL Bypass Mode Control B/D/F/Type: Address Offset: Default Value: Access: Size: This register controls WDLL functional and bypass modes for all the buffer types. 6.2.60 C0WDLLCMC - Channel 0 WDLL/Clock Macro Clock Control B/D/F/Type: Address Offset: ...
Page 155
Device 0 Memory Mapped I/O Register 6.2.62 C1WL0REOST - Channel 1 WL0 RCVENOUT Slave Timing B/D/F/Type: Address Offset: Default Value: Access: Size: This register can be locked by the Global RCOMP Lock bit (GBRCOMPCTL[31]). 6.2.63 C1WL1REOST - Channel 1 WL1 ...
Page 156
C1WDLLCMC - Channel 1 WDLL/Clock Macro Clock Control B/D/F/Type: Address Offset: Default Value: Access: Size: This register controls WDLL and Macro Clock Control. 6.2.67 C1HCTC - Channel 1 Half Clock Timing Control B/D/F/Type: Address Offset: Default Value: Access: Size: ...
Page 157
Device 0 Memory Mapped I/O Register 6.2.67.1 GBRCOMPCTL - Global/System Memory RCOMP Control B/D/F/Type: Address Offset: Default Value: Access: Size: This register controls the Global and System Memory RCOMP feature. Bit Access 31 R/W/L 30:24 R/W/L 23 R/W/L 24 R/W/L ...
Page 158
C0DRAMW - Channel 0 DRAM Width B/D/F/Type: Address Offset: Default Value: Access: Size: This register determines the width of SDRAM devices populated in each rank of memory in this channel. Bit Access 15:8 RO 7:6 R/W/L 5:4 R/W/L 3:2 ...
Page 159
Device 0 Memory Mapped I/O Register 6.2.70 G2SC - Group 2 Strength Control B/D/F/Type: Address Offset: Default Value: Access: Size: 6.2.71 G3SC - Group 3 Strength Control B/D/F/Type: Address Offset: Default Value: Access: Size: 6.2.72 G4SC - Group 4 Strength ...
Page 160
C1DRAMW - Channel 1 DRAM Width B/D/F/Type: Address Offset: Default Value: Access: Size: This register determines the width of SDRAM devices populated in each rank of memory in this channel. Bit Access 15:8 RO 7:6 R/W/L 5:4 R/W/L 3:2 ...
Page 161
Device 0 Memory Mapped I/O Register 6.2.78 G1SRPUT - Group 1 Slew Rate Pull-up Table B/D/F/Type: Address Offset: Default Value: Access: Size: This register can be locked by the Global RCOMP Lock bit (GBRCOMPCTL[31]). 6.2.79 G1SRPDT - Group 1 Slew ...
Page 162
G3SRPUT - Group 3 Slew Rate Pull-up Table B/D/F/Type: Address Offset: Default Value: Access: Size: This register can be locked by the Global RCOMP Lock bit (GBRCOMPCTL[31]). 6.2.83 G3SRPDT - Group 3 Slew Rate Pull-Down Table B/D/F/Type: Address Offset: ...
Page 163
Device 0 Memory Mapped I/O Register 6.2.86 G5SRPUT - Group 5 Slew Rate Pull-up Table B/D/F/Type: Address Offset: Default Value: Access: Size: This register can be locked by the Global RCOMP Lock bit (GBRCOMPCTL[31]). 6.2.87 G5SRPDT - Group 5 Slew ...
Page 164
G7SRPUT - Group 7 Slew Rate Pull-up Table B/D/F/Type: Address Offset: Default Value: Access: Size: This register can be locked by the Global RCOMP Lock bit (GBRCOMPCTL[31]). 6.2.91 G7SRPDT - Group 7 Slew Rate Pull-Down Table B/D/F/Type: Address Offset: ...
Page 165
Device 0 Memory Mapped I/O Register 6.3 Device 0 MCHBAR Clock Controls Table 5. Device 0 MCHBAR Clock Controls Register Name Clocking Configuration Reserved Unit Power Management Control 1 CP Unit Control Reserved Sticky Scratchpad Data Reserved Unit Power Management ...
Page 166
CLKCFG - Clocking Configuration B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access 31 R/W 30:28 RO 27:18 R 16:14 R R/W/L 11:8 R/W 7:7 R/W/L 6:4 RO 3:3 RO 2:0 RO 6.3.2 UPMC1 ...
Page 167
Device 0 Memory Mapped I/O Register 6.3.3 CPCTL - CPunit Control B/D/F/Type: Address Offset: Default Value: Access: Size: 6.3.4 SSKPD - Sticky Scratchpad Data B/D/F/Type: Address Offset: Default Value: Access: Size: This register holds 16 writable bits with no functionality ...
Page 168
... Device 0 MCHBAR Thermal Management Controls Note: The Mobile Intel 945GM/GME/PM/GMS/GU/GSE, 943/940GML and Intel 945GT Express Chipsets have two internal thermal sensors. The set of registers from MCHBAR Offset C88h to C9F correspond to Thermal Sensor 1 and the set of registers from MCHBAR Offset CD8 to CE6 correspond to Thermal Sensor 2 respectively. ...
Page 169
Device 0 Memory Mapped I/O Register Table 6. Device 0 MCHBAR Thermal Management Controls (Sheet Register Register Name Symbol TCO Fuses 0 TCOF0 Thermal Interrupt Status TIS0 Thermal Sensor Temperature TSTTP0-2 Trip Point Register Thermal Error Command ...
Page 170
TSC1 - Thermal Sensor Control 1 B/D/F/Type: Address Offset: Default Value: Access: Size: This register controls the operation of the internal thermal sensor located in the memory hot spot. Bit Access 7:7 R/W/L 6:6 R/W 5:2 R/W 1:1 R/W/L ...
Page 171
Device 0 Memory Mapped I/O Register 6.4.2 TSS1 - Thermal Sensor Status1 B/D/F/Type: Address Offset: Default Value: Access: Size: This read only register provides trip point information and status of the thermal sensor. Bit Access 7:7 RO 6:6 RO 5:5 ...
Page 172
TR1 - Thermometer Read1 B/D/F/Type: Address Offset: Default Value: Access: Size: This register generally provides the calibrated current temperature from the thermometer circuit when the Thermometer mode is enabled. Bit Access 7:0 RO 6.4.4 TSTTP1 - Thermal Sensor Temperature ...
Page 173
Device 0 Memory Mapped I/O Register 6.4.5 TCO1 - Thermal Calibration Offset1 B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access 7:7 R/WO 6:0 R/W/L Datasheet 0/0/0/MCHBAR C92h _0xxx__xxxx_h R/WO; R/W/L 8 bits Default Value Lock bit for Catastrophic (LBC): ...
Page 174
THERM1-1 - Hardware Throttle Control 1-1 B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access 7:7 R/W/L 6:5 RO 4:4 R/W/L 3:3 R/W/L 2:2 R/W/L 1:1 R/W/L 0:0 R/WO 174 0/0/0/MCHBAR C94h 00h R/W/L; ROR/WO 8 bits Default Value ...
Page 175
Device 0 Memory Mapped I/O Register 6.4.7 TCOF1 – TCO Fuses 1 B/D/F/Type: Address Offset: Default Value: Access: Size: This register indicates the fuse settings for the TCO register. TCO has 7 bits, which are set by fuses when trimmed. ...
Page 176
TIS1 - Thermal Interrupt Status 1 B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access 15:10 RO 9:9 R/WC 8:8 R/WC 7:7 R/WC 6:6 R/WC 5:5 R/WC 4:4 R/WC 3:3 R/WC 176 0/0/0/MCHBAR C9A-C9Bh 0000h R/WC bits ...
Page 177
Device 0 Memory Mapped I/O Register Bit Access 2:2 R/WC 1:1 R/WC 0:0 R/WC 6.4.9 TSTTP1-2 – Thermal Sensor Temperature Trip Point 1-2 B/D/F/Type: Address Offset: Default Value: Access: Size: This register sets the target values for some of the ...
Page 178
IUB - In Use Bits B/D/F/Type: Address Offset: Default Value: Access: Size: Semaphore bits available for software. Bit Access 31:25 RO 24:24 RS/WC 23:17 RO 16:16 RS/WC 15:9 RO 178 Device 0 Memory Mapped I/O Register 0/0/0/MCHBAR CD0-CD3h 00000000h ...
Page 179
Device 0 Memory Mapped I/O Register Bit Access 8:8 RS/WC 7:1 RO 0:0 RS/WC Datasheet Default Description Value In Use Bit 1 (IU1): Software semaphore bit. After a full (G)MCH RESET, a read to this bit returns a 0. After ...
Page 180
TSC0-1 - Thermal Sensor Control 0-1 B/D/F/Type: Address Offset: Default Value: Access: Size: This register controls the operation of the internal thermal sensor located in the memory hot spot. Bit Access 7:7 R/W/L 6:6 R/W 5:2 R/W 1:1 R/W/L ...
Page 181
Device 0 Memory Mapped I/O Register 6.4.12 TSS0 - Thermal Sensor Status0 B/D/F/Type: Address Offset: Default Value: Access: Size: This read only register provides trip point information and status of the thermal sensor. Bit Access 7:7 RO 6:6 RO 5:5 ...
Page 182
TR0 - Thermometer Read 0 B/D/F/Type: Address Offset: Default Value: Access: Size: This register generally provides the calibrated current temperature from the thermometer circuit when the Thermometer mode is enabled. See the temperature tables for the temperature calculations. Bit ...
Page 183
Device 0 Memory Mapped I/O Register Bit Access 15:8 R/W/L 7:0 R/W/L 6.4.15 TCO0 - Thermal Calibration Offset0 B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access 7:7 R/WO 6:0 R/W/L Datasheet Default Value Hot Trip Point Setting (HTPS): 00h ...
Page 184
THERM0-1 - Hardware Throttle Control 0-1 B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access 7:7 R/W/L 6:5 RO 4:4 R/W/L 3:3 R/W/L 2:2 R/W/L 1:1 R/W/L 0:0 R/WO 184 0/0/0/MCHBAR CE4h 00h R/W/L; ROR/WO 8 bits Default Value ...
Page 185
Device 0 Memory Mapped I/O Register 6.4.17 TCOF0 – TCO Fuses 0 B/D/F/Type: Address Offset: Default Value: Access: Size: This register indicates the fuse settings for the TCO register. TCO has 7 bits, which are set by fuses when trimmed. ...
Page 186
TIS 0- Thermal Interrupt Status 0 B/D/F/Type: Address Offset: Default Value: Access: Size: This register is used to report which specific error condition resulted in the D2F0 or D2F1 ERRSTS[Thermal Sensor event for SMI/SCI/SERR] or memory mapped IIR Thermal ...
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Device 0 Memory Mapped I/O Register Bit Access 3:3 R/WC 2:2 R/WC 1:1 R/WC 0:0 R/WC 6.4.19 TSTTP0-2 - Thermal Sensor Temperature Trip Point Register 0-2 B/D/F/Type: Address Offset: Default Value: Access: Size: This register sets the target values for ...
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Bit Access 15:8 R/W/L 7:0 R/W/L 6.4.20 TERRCMD - Thermal Error Command B/D/F/Type: Address Offset: Default Value: Access: Size: This register select which errors are generate a SERR DMI interface special cycle, as enabled by ERRCMD [SERR Thermal Sensor event].The ...
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Device 0 Memory Mapped I/O Register 6.4.21 TSMICMD - Thermal SMI Command B/D/F/Type: Address Offset: Default Value: Access: Size: This register selects specific errors to generate a SMI DMI cycle, as enabled by the SMI Error Command register[SMI on Thermal ...
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TSCICMD - Thermal SCI Command B/D/F/Type: Address Offset: Default Value: Access: Size: This register selects specific errors to generate a SCI DMI cycle, as enabled by the SCI Error Command register [SCI on Thermal Sensor Trip].The SCI and SERR ...
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Device 0 Memory Mapped I/O Register 6.4.23 TINTRCMD - Thermal INTR Command B/D/F/Type: Address Offset: Default Value: Access: Size: This register selects specific errors to generate an INT DMI cycle. Bit Access 7:5 RO 4:4 R/W 3:3 R/W 2:2 R/W ...
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Bit Access 5:5 R/W/L 4:4 R/W/L 3:3 RO 2:2 RO 1:1 RO 0:0 R/W 6.4.25 DFT_STRAP1 – DFT Register B/D/F/Type: Address Offset: Default Value: _0xxx__xx0x__xxxx__xxxx__xxxx__xxxx__xxxx__xxxx_h Access: Size: 192 (Sheet Default Description Value EXTTS1 Action Select (AS1): Lockable ...
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... ECO Bits 6.5.1 Power Management Mode Support Options The Mobile Intel 945GM/GME/PM/GMS/GU/GSE, 943/940GML and Intel 945GT Express Chipsets have added the capability to support C state power management modes. This allows the option to support CPU PM from either the (G)MCH or ICH7M. Both cannot be implemented at the same time ...
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C2C3TT - Transition Timer B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access 31:19 RO 18:7 R/W 6:0 RO 6.5.3 C3C4TT - Transition Timer B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access ...
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Device 0 Memory Mapped I/O Register 6.5.4 MIPMC4 - Memory Interface Power Management Control 4 B/D/F/Type: Address Offset: Default Value: Access: Size: 6.5.5 MIPMC5 - Memory Interface Power Management Control 5 B/D/F/Type: Address Offset: Default Value: Access: Size: 6.5.6 MIPMC6 ...
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PMCFG - Power Management Configuration B/D/F/Type: Address Offset: Default Value: BIOS Optimal Default Access: Size: Bit Access 31 R 29:5 RO; R R/W 1:0 R/W 196 0/0/0/MCHBAR F10-F13h 00040000h 0h R/W; RO ...
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Device 0 Memory Mapped I/O Register 6.5.9 SLFRCS - Self-Refresh Channel Status B/D/F/Type: Address Offset: Default Value: Access: Size: This register is reset by PWROK only. Bit Access 31 R/WC 0 R/WC 6.5.10 GIPMC1 - Graphics Interface Power ...
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UPMC3 Unit Power Management Control 3 B/D/F/Type: Address Offset: Default Value: Access: Size: 6.5.13 ECO - ECO Bits B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access 32:19 R/W; RO 0000000000b 18 R R/W ...
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Device 0 Memory Mapped I/O Register 6.6 DMI RCRB This section describes the mapped registers for the DMI. The DMIBAR register, described in Section This Root Complex Register Block (RCRB) controls the (G)MCH-ICH7-M serial interconnect. An RCRB is required for ...
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Table 8. DMI RCB (Sheet Register Name DMI Link Control DMI Link Status Reserved DMI Control 1 Reserved DMI Control 2 Reserved DMI DRC configuration 6.6.1 DMIVCECH - DMI Virtual Channel Enhanced Capability B/D/F/Type: Address Offset: Default ...