QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 262

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

7.1.44
7.1.45
7.1.46
262
PEGLC - PCI Express-G Legacy Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register controls functionality that is needed by Legacy (non-PCI Express aware)
OS's during run time.
PEGCTL1 – PEG Control 1
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register must be accessed with DWORD granularity and not with BYTE granularity.
PEGTCFG – PEG Timing Configuration
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
31:3
Bit
2
1
0
Access
R/W
R/W
R/W
RO
00000000h
Default
Value
0b
0b
0b
Reserved
PME GPE Enable (PMEGPE):
(Assert_PMEGPE and deassert_PMEGPE messages on DMI). This
enables the MCH to support PMEs on the PEG port under legacy
OSs.
Hot Plug GPE Enable (HPGPE):
event is received.
received (Assert_HPGPE and deassert_HPGPE messages on
DMI). This enables the MCH to support Hot Plug on the PEG port
under legacy OSs.
General Message GPE Enable (GENGPE):
general GPE message can be received via the PEG port from an
external Intel® device (i.e., PxH) and will be subsequently
forwarded to the ICH (via Assert_GPE and deassert_GPE
messages on DMI). For example, PxH might send this message
if a PCI Express* device is hot plugged into a PxH downstream
port.
0: Do not generate GPE PME message when PME is received.
1: Generate a GPE PME message when PME is received
0: Do not generate GPE Hot Plug message when Hot Plug
1: Generate a GPE Hot Plug message when Hot Plug Event is
0: Do not forward received GPE assert/deassert messages.
1: Forward received GPE assert/deassert messages. These
PCI Express Graphics Device 1 Configuration Registers (D1:F0)
0/1/0/PCI
EC-EFh
00000000h
R/W; RO
32 bits
0/1/0/PCI
F0-F3h
00010000h
R/W; RO
32 bits
0/1/0/MMR
E80-E83h
08080488h
R/WC; RO
32 bits
Description
Datasheet