QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 255

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

PCI Express Graphics Device 1 Configuration Registers (D1:F0)
7.1.37
Datasheet
LCTL - Link Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register allows control of PCI Express link.
15:8
1:0
Bit
7
6
5
4
3
2
R/W/SC
Access
R/W
R/W
R/W
R/W
RO
RO
RO
Default
Value
000h
00b
0b
0b
0b
0b
0b
0b
Reserved
Reserved
Common Clock Configuration (CCC):
opposite end of this Link are operating with asynchronous
reference clock.
opposite end of this Link are operating with a distributed common
reference clock.
The state of this bit affects the L0s Exit Latency reported in
LCAP[14:12] and the N_FTS value advertised during link training.
See PEGL0SLAT at offset 224h.
Retrain Link (RL):
Layer LTSSM from L0, L0s, or L1 states to the Recovery state.
This bit always returns 0 when read.
This bit is cleared automatically (no need to write a 0).
Link Disable (LD):
Disabled state (via Recovery) from L0, L0s, or L1 states. Link
retraining happens automatically on 0 to 1 transition, just like
when coming out of reset.
Writes to this bit are immediately reflected in the value read from
the bit, regardless of actual Link state.
Read Completion Boundary (RCB):
Hardwired to 0 to indicate 64 bytes.
Reserved
Active State PM (ASPM):
Controls the level of active state power management supported
on the given link.
0: Indicates that this component and the component at the
1: Indicates that this component and the component at the
0: Normal operation.
1: Full Link retraining is initiated by directing the Physical
0: Normal operation
1: Link is disabled. Forces the LTSSM to transition to the
00:
01:
10:
11:
Disabled
L0s Entry Supported
Reserved
L0s and L1 Entry Supported
0/1/0/PCI
B0-B1h
0000h
R/W; ROR/W/SC
16 bits
Description
255