QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 191

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

Device 0 Memory Mapped I/O Register
6.4.23
6.4.24
Datasheet
TINTRCMD - Thermal INTR Command
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register selects specific errors to generate an INT DMI cycle.
EXTTSCS - External Thermal Sensor Control and Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
7:5
4:4
3:3
2:2
1:1
0:0
7:7
6:6
Bit
Bit
Access
Access
R/W
R/W
R/W
R/W
R/W
R/W/L
R/WO
RO
Default
Value
Default
0h
0b
0b
0b
0b
0b
Value
0b
0b
Reserved
Reserved
INTR on Aux1 Thermal Sensor Trip:
1 = An INTR DMI cycle is generated by (G)MCH
INTR on Catastrophic Thermal Sensor Trip:
1 = An INTR DMI cycle is generated by (G)MCH
INTR on Hot Thermal Sensor Trip:
1 = An INTR DMI cycle is generated by (G)MCH
INTR on Aux0 Thermal Sensor Trip:
1 = An INTR DMI cycle is generated by (G)MCH
External Sensor Enable:
Setting this bit to 1 locks the lockable bits in this register. This
bit may only be set to a 0 by a hardware reset. Once locked,
writing a 0 to bit has no effect.
If both internal sensor throttling and external write sensor
throttling are enabled, either can initiate throttling.
Throttling Type Select (TTS):
Lockable by EXTTSCS [External Sensor Enable].
If External Thermal Sensor Enable = 1, then
0 = DRAM throttling based on the settings in the Device 0
MCHBAR Dram Throttling Control register
1 = (G)MCH throttling, based on the settings in the Device 0
MCHBAR
0 = External Sensor input is disabled.
1 = External Sensor input is enabled.
0/0/0/MCHBAR
CF3h
00h
R/W; RO
8 bits
0/0/0/MCHBAR
CFFh
00h
R/WO; R/W/L; RO
8 bits
(Sheet 1 of 2)
Description
Description
191