QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 97

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

Host Bridge Device 0 - Configuration Registers (D0:F0)
5.1.20
Datasheet
PAM2 - Programmable Attribute Map 2
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register controls the read, write, and shadowing attributes of the BIOS areas from
0C8000h-0CFFFFh.
1:0
7:6
5:4
3:2
1:0
Bit
Bit
Access
Access
R/W/L
R/W/L
R/W/L
RO
RO
Default
Default
Value
Value
00b
00b
00b
00b
00b
0C0000h-0C3FFFh Attribute (LOENABLE):
This field controls the steering of read and write cycles that
address the BIOS area from 0C0000h to 0C3FFFh.
00: DRAM Disabled: Accesses are directed to DMI.
01: Read Only: All reads are serviced by DRAM. All writes are
forwarded to DMI.
10: Write Only: All writes are sent to DRAM. Reads are serviced
by DMI.
11: Normal DRAM Operation: All reads and writes are serviced by
DRAM.
Reserved
0CC000h-0CCFFFh Attribute (HIENABLE):
This field controls the steering of read and write cycles that
address the BIOS area from 0CC000h to 0CCFFFh.
00:DRAM Disabled: Accesses are directed to DMI.
01:Read Only: All reads are serviced by DRAM. All writes are
forwarded to DMI.
10:Write Only: All writes are sent to DRAM. Reads are serviced by
DMI.
11:Normal DRAM Operation: All reads and writes are serviced by
DRAM.
Reserved
0C8000h-0CBFFFh Attribute (LOENABLE):
This field controls the steering of read and write cycles that
address the BIOS area from 0C8000h to 0CBFFFh.
00: DRAM Disabled: Accesses are directed to DMI.
01: Read Only: All reads are serviced by DRAM. All writes are
forwarded to DMI.
10: Write Only: All writes are sent to DRAM. Reads are serviced
by DMI.
11: Normal DRAM Operation: All reads and writes are serviced by
DRAM.
0/0/0/PCI
92h
00h
R/W/L; RO
8 bits
Description
Description
97