QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 38

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

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HHITM#
HLOCK#
HREQ[4:0]#
HTRDY#
HRS[2:0]#
HDPWR#
HCPUSLP#
Signal Name
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
CMOS
Type
I/O
I/O
I/O
2X
O
O
O
I
Host Hit Modified:
Indicates that a caching agent holds a modified version of the
requested line and that this agent assumes responsibility for
providing the line.
Also, driven in conjunction with HIT# to extend the snoop
window.
Host Lock:
All CPU bus cycles sampled with the assertion of HLOCK# and
HADS#, until the negation of HLOCK# must be atomic, i.e., PCI
Express graphics access to System Memory is allowed when
HLOCK# is asserted by the CPU.
Host Request Command:
Defines the attributes of the request. HREQ[4:0]# are
transferred at 2x rate. Asserted by the requesting agent during
both halves of the Request Phase. In the first half the signals
define the transaction type to a level of detail that is sufficient to
begin a snoop request. In the second half the signals carry
additional information to define the complete transaction type.
Host Target Ready:
Indicates that the target of the processor transaction is able to
enter the data transfer phase.
Host Response Status:
Indicates the type of response according to the following the
table:
HRS[2:0]#
000
001
010
011
100
101
110
111
Host Data Power:
Used by (G)MCH to indicate that a data return cycle is pending
within 2 HCLK cycles or more. CPU uses this signal during a
read-cycle to activate the data input buffers in preparation for
HDRDY# and the related data.
Host CPU Sleep:
When asserted in the Stop-Grant state, causes the processor to
enter the Sleep state. During Sleep state, the processor stops
providing internal clock signals to all units, leaving only the
Phase-Locked Loop (PLL) still operating. Processors in this state
will not recognize snoops or interrupts.
Idle state
Retry response
Deferred response
Reserved (not driven by (G)MCH)
Hard Failure (not driven by (G)MCH)
No data response
Implicit Write back
Normal data response
Response type
Description
Signal Description
Datasheet