QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 170

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

6.4.1
170
TSC1 - Thermal Sensor Control 1
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register controls the operation of the internal thermal sensor located in the
memory hot spot.
7:7
6:6
5:2
1:1
0:0
Bit
Access
R/W/L
R/W/L
R/W
R/W
N/A
Default
Value
0000b
0b
0b
0b
0b
Thermal Sensor Enable (TSE):
This bit enables power to the thermal sensor. Lockable via TCO
bit 7.
0 = Disabled
1 = Enabled
Reserved
Digital Hysteresis Amount (DHA):
This bit determines whether no offset, 1 LSB, 2... 15 is used for
hysteresis for the trip points.
0001 = 1 TR value added to each trip temperature when tripped
0010 = 2 TR values added to each trip temperature when
tripped
...
0110 ~3.0°C (Recommended setting)
...
1110= 14 TR value added to each trip temperature when
tripped
1111 = 15 TR values added to each trip temperature when
tripped
Note: TR = Temperature Read
Reserved
In Use (IU):
Software semaphore bit. After a full MCH RESET, a read to this
bit returns a 0. After the first read, subsequent reads will return
a 1. A write of a 1 to this bit will reset the next read value to 0.
Software can poll this bit until it reads a 0, and will then own the
usage of the thermal sensor.
Writing a 0 to this bit has no effect.
0/0/0/MCHBAR
C88h
00h
R/W/L
8 bits
Description
Device 0 Memory Mapped I/O Register
Datasheet