QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 103

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

Host Bridge Device 0 - Configuration Registers (D0:F0)
5.1.26
Note:
Datasheet
TOLUD - Top of Low Used DRAM Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This 8-bit register defines the Top of Usable Dram. Graphics Stolen Memory and TSEG
are within dram space defined under TOLUD. From the top of low used dram, (G)MCH
claims 1 to 64 MBs of DRAM for internal graphics if enabled and 1, 2 or 8 MBs of DRAM
for TSEG if enabled.
Even if the OS does not need any PCI space, TOLUD can only be programmed to FFh.
This ensures that addresses within 128 MB below 4 GB that are reserved for APIC.
7:3
2:0
Bit
Access
R/W/L
RO
Default
Value
01h
00b
Top of Low Usable DRAM (TOLUD):
This register contains bits 31 to 27 of an address one byte above
the maximum DRAM memory that is usable by the operating
system. Address bits [31:27] programmed to a “01h” implies a
minimum memory size of 128 MBs.
Configuration software must set this value to the smaller of the
following 2 choices
Address bits 26:0 are assumed to be 000_0000h for the
purposes of address comparison. The host interface positively
decodes an address towards dram if the incoming address is less
than that value programmed in this register.
This register must not be set to 0000 0 b.
The Top of Usable DRAM is the lowest address above both
Graphics Stolen memory and TSEG. The host interface
determines the base of Graphics Stolen memory by subtracting
the graphics stolen memory size from TOLUD and further
decrements by TSEG size to determine base of TSEG.
Reserved
- maximum amount memory in the system
- Minimum address allocated for PCI memory.
0/0/0/PCI
9Ch
08h
R/W/L; RO
8 bits
Description
103