QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 332

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

9.6
Note:
9.6.1
Table 19.
332
System Management Mode (SMM)
System Management Mode uses main memory for System Management RAM (SMM
RAM). The (G)MCH supports: Compatible SMRAM (C_SMRAM), High Segment (HSEG),
and Top of Memory Segment (TSEG). System Management RAM space provides a
memory area that is available for the SMI handlers and code and data storage. This
memory resource is normally hidden from the system OS so that the processor has
immediate access to this memory space upon entry to SMM. (G)MCH provides three
SMRAM options:
The above 1-MB solutions require changes to compatible SMRAM handlers code to
properly execute above 1 MB.
DMI and PCI Express masters are not allowed to access the SMM space.
SMM Space Definition
SMM space is defined by its addressed SMM space and its DRAM SMM space. The
addressed SMM space is defined as the range of bus addresses used by the CPU to
access SMM space. DRAM SMM space is defined as the range of physical DRAM memory
locations containing the SMM code. SMM space can be accessed at one of three
transaction address ranges: Compatible, High and TSEG. The Compatible and TSEG
SMM space is not remapped and therefore the addressed and DRAM SMM space is the
same address range. Since the High SMM space is remapped the addressed and DRAM
SMM space are different address ranges. Note that the High DRAM space is the same as
the Compatible Transaction Address space.
ranges:
These abbreviations are used later in the table describing SMM Space Transaction
Handling.
SMM Space Definition Summary
• Below 1-MB option that supports compatible SMI handlers.
• Above 1-MB option that allows new SMI handlers to execute with write-back
• Optional TSEG area of 1 MB, 2 MB, or 8 MB in size. The TSEG area lies below IGD
• Compatible Transaction Address (Adr C)
• High Transaction Address (Adr H)
• TSEG Transaction Address (Adr T)
cacheable SMRAM.
stolen memory.
SMM Space Enabled
Compatible (C)
TSEG (T)
High (H)
Transaction Address Space
FEDA_0000h to FEDB_FFFFh
000A_0000h to 000B_FFFFh
(TOLUD-STOLEN-TSEG) to
TOLUD-STOLEN
Table 19
describes three unique address
000A_0000h to 000B_FFFFh
000A_0000h to 000B_FFFFh
(TOLUD-STOLEN-TSEG) to
DRAM Space (DRAM)
TOLUD-STOLEN
System Address Map
Datasheet