QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 55

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

Signal Description
2.10
Table 2.
2.10.1
Datasheet
Reset States and Pull-up / Pull-downs
This section describes the expected states of the (G)MCH I/O buffers during and
immediately after the assertion of RSTIN#. This table only refers to the contributions
on the interface from the (G)MCH and does not reflect any external influence (such as
external pull-up/pull-down resistors or external drivers.
Legend
Host Interface Signals
Unless otherwise noted, the voltage level for all signals in this interface is tied to the
termination voltage of the host bus (VTT).
DRIVE
N/A
IN
TRI
PU
PD
STRAP
HADS#
HBNR#
HBPRI#
HBREQ0#
HCPURST#
HDBSY#
HDEFER#
HDINV[3:0]#
HDRDY#
HA[31:3]#
HADSTB[1:0]#
HD[63:2]#
Signal Name
Strong drive to 0 or 1 (to normal value supplied by the core logic if not otherwise
stated)
Value is indeterminate
Input buffer enabled
Tri-state (Signals are not driven)
Weak internal pull-up
Weak internal pull-down
Value is determined by the strap setting
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
State during
Assertion
(Sheet 1 of 2)
RSTIN#
DRIVE 0
N/A
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
Deassertion
State after
RSTIN#
DRIVE 0
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
DRIVE 0
DRIVE 0
N/A
S3
PU
PU
PU
PU
PU
PU
PU
PU
PU
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