QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 88

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

5.1.12
88
EPBAR - Egress Port Base Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This is the base address for the Egress Port Root Complex MMIO configuration space.
This window of addresses contains the Egress Port Root Complex register set for the
PCI Express Hierarchy associated with the MCH. There is no physical memory within
this 4-KB window that can be addressed. The 4 KB reserved by this register does not
alias to any conventional PCI 2.3-compliant memory mapped space.
On reset, this register is disabled and must be enabled by writing a 1 to bit[0] of this
register.
31:12
11:1
Bit
0
Access
R/W/L
R/W/L
RO
Default
00000h
Value
000h
0b
Egress Port RCRB Base Address:
This field corresponds to bits 31 to 12 of the base address
Egress port RCRB MMIO configuration space.
BIOS will program this register resulting in a base address for a
4-KB block of contiguous memory address space. This register
ensures that a naturally aligned 4-KB space is allocated within
total addressable memory space of 4 GB.
System Software uses this base address to program the Egress
Port RCRB and associated registers.
Reserved
EPBAR Enable (EPBAREN):
0: EPBAR is disabled and does not claim memory.
1: EPBAR memory mapped accesses are claimed and decoded
appropriately.
0/0/0/PCI
40-43h
00000000h
R/W/L; RO
32 bits
Host Bridge Device 0 - Configuration Registers (D0:F0)
Description
Datasheet