QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 209

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

Device 0 Memory Mapped I/O Register
6.6.13
Datasheet
DMILCTL - DMI Link Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register allows control of DMI.
14:12
11:10
15:8
9:4
3:0
6:2
Bit
Bit
7
Access
Access
R/WO
R/W
RO
RO
RO
RO
RO
Default
Default
Value
Value
010b
11b
04h
00h
00h
1h
0b
L0s Exit Latency (L0SELAT):
Indicates the length of time this Port requires to complete the
transition from L0s to L0.
Active State Link PM Support (ASLPMS):
L0s & L1 entry supported.
Max Link Width (MLW):
Indicates the maximum number of lanes supported for this link.
Max Link Speed (MLS):
Hardwired to indicate 2.5 Gb/s.
Reserved
Extended Synch (EXTSYNC):
in the L0s state followed by a single SKP Ordered Set prior to
entering L0, and the transmission of 1024 TS1 ordered sets in
the RecoveryRcvrLock state prior to entering the
RecoveryRcvrCfg state.
This mode provides external devices monitoring the link time
to achieve bit and symbol lock before the link enters L0 state
and resumes communication. This is a test mode only and may
cause other undesired side effects such as buffer overflows or
underruns.
Reserved
000:Less than 64 ns
001:64 ns to less than 128 ns
010:128 ns to less than 256 ns
011:256 ns to less than 512 ns
100:512 ns to less than 1 µs
101:1 µs to less than 2 µs
110:2 µs-4 µs
111:More than 4 µs
0: Standard Fast Training Sequence (FTS).
1: Forces extended transmission of 4096 FTS ordered sets
0/0/0/DMIBAR
88-89h
0000h
R/W; RO
16 bits
Description
Description
209