QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 146

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

6.2.40
146
C1GTC - Channel 1 (G)MCH Throttling Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register contains programmable Event weights that are input into the averaging
filter. Each Event weight is a normalized 8-bit value that the BIOS must program. The
BIOS must account for burst length, 1N/2N rule considerations. It is also possible for
BIOS to take into account type loading variations of memory caused as a function of
memory types and population of ranks.
31:31
30:30
29:29
28:25
24:22
21:21
20:20
19:19
18:16
15:8
7:0
Bit
Access
R/W/L
R/W/L
R/W/L
R/W/L
R/W/L
R/W/L
R/W/L
R/W/L
RO
RO
RO
Default
Value
000b
000b
00h
00h
0b
0b
0b
0h
0b
0b
0b
(G)MCH Throttle Lock (GTLOCK):
This bit secures the (G)MCH throttling control registers GTEW and
GTC. This bit defaults to 0. Once a 1 is written to this bit, all of the
configuration register bits are read-only.
Reserved
Reserved
Reserved
Reserved
(G)MCH Bandwidth Based Throttling Enable:
0 = Bandwidth Threshold (WAB) is not used for throttling.
1 = Bandwidth Threshold (WAB) is used for throttling.
If both Bandwidth based and thermal sensor based throttling
modes are on when the thermal sensor trips, the Thermal
threshold is used for throttling.
(G)MCH Thermal Sensor Trip Enable:
0 = (G)MCH throttling is not initiated when the (G)MCH thermal
sensor trips.
1 = (G)MCH throttling is initiated when the (G)MCH thermal
sensor trips and the Filter output is equal to or exceeds thermal
threshold WAT.
Reserved
Reserved
WAB:
Threshold allowed per clock for bandwidth based throttling.
(G)MCH does not allow transactions to proceed on the DDR bus if
the output of the filter equals or exceeds this value.
WAT:
Threshold allowed per clock during thermal sensor enabled
throttling. (G)MCH does not allow transactions to proceed on the
DDR bus if the output of the filter equals or exceeds this value.
0/0/0/MCHBAR
1C4-1C7h
00000000h
R/W/L; RO
32 bits
Description
Device 0 Memory Mapped I/O Register
Datasheet