QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 208

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

6.6.11
6.6.12
208
DMILE2A - DMI Link Entry 2 Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Second part of a Link Entry which declares an internal link to another Root Complex
Element.
DMILCAP - DMI Link Capabilities
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register indicates DMI specific capabilities.
63:32
31:12
31:18
17:15
11:0
Bit
Bit
Access
Access
R/WO
R/WO
RO
RO
RO
00000000
Default
00000h
Default
Value
000h
Value
0000h
010b
h
Reserved
Link Address (LA):
Memory mapped base address of the RCRB that is the target
element (Egress Port) for this link entry.
Reserved
Reserved
L1 Exit Latency (L1SELAT):
Indicates the length of time this Port requires to complete the
transition from L1 to L0. The value 010 b indicates the range of
2 µs to less than 4 µs.
Both bytes of this register that contain a portion of this field
must be written simultaneously in order to prevent an
intermediate (and undesired) value from ever existing.
000:Less than 1 µs
001:1 µs to less than 2 µs
010:2 µs to less than 4 µs
011:4 µs to less than 8 µs
100:8 µs to less than 16 µs
101:16 µs to less than 32 µs
110:32 µs-64 µs
111:More than 64 µs
0/0/0/DMIBAR
68-6Fh
0000000000000000h
R/WO; RO
64 bits
0/0/0/DMIBAR
84-87h
00012C41h
R/WO; RO
32 bits
Description
Description
Device 0 Memory Mapped I/O Register
Datasheet