QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 270
QG82945GSE S LB2R
Manufacturer Part Number
QG82945GSE S LB2R
Description
GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
Manufacturer
Intel
Datasheet
1.AU80586GE025DSLB73.pdf
(482 pages)
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7.2.11
7.2.12
270
LE1A - Link Entry 1 Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register is the second part of a Link Entry which declares an internal link to
another Root Complex Element.
PEGTC - PCI Express-G Timeout Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
63:32
31:12
11:0
Bit
Access
R/WO
RO
RO
00000000h
Default
00000h
Value
000h
Reserved
Link Address (LA):
Memory mapped base address of the RCRB that is the target
element (Egress Port) for this link entry.
Reserved
PCI Express Graphics Device 1 Configuration Registers (D1:F0)
0/1/0/MMR
158-15Fh
0000000000000000h
R/WO; RO
64 bits
0/1/0/MMR
204-207h
00000CF4h
R/W; RO
32 bits
Description
Datasheet
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