QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 142

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

6.2.26
6.2.27
6.2.28
6.2.29
6.2.30
142
C0ODT - Channel 0 ODT Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
The register fields allow control of DRAM and MCH ODT.
C1DRB0 - Channel 1 DRAM Rank Boundary Address 0
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
The operation of this register is detailed in the description for register C0DRB0.
C1DRB1 - Channel 1 DRAM Rank Boundary Address 1
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
The operation of this register is detailed in the description for register C0DRB0.
C1DRA0 - Channel 1 DRAM Rank 0,1 Attribute
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
The operation of this register is detailed in the description for register C0DRA0.
C1DCLKDIS - Channel 1 DRAM Clock Disable
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
The operation of this resister is detailed in the description for register C0DCLKDIS.
0/0/0/MCHBAR
168-16Fh
0002879822049200h
R/W; RO
64 bits
0/0/0/MCHBAR
180h
00h
R/W
8 bits
0/0/0/MCHBAR
181h
00h
R/W
8 bits
0/0/0/MCHBAR
188h
00h
R/W; RO
8 bits
0/0/0/MCHBAR
18Ch
00h
R/W; RO
8 bits
Device 0 Memory Mapped I/O Register
Datasheet