QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 232

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

7.1.6
7.1.7
232
CC1 - Class Code
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register identifies the basic function of the device, a more specific sub-class, and a
register- specific programming interface.
CL1 - Cache Line Size
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
23:16
15:8
7:0
7:0
Bit
Bit
Access
Access
R/W
RO
RO
RO
Default
Default
Value
Value
06h
04h
00h
00h
Base Class Code (BCC):
Indicates the base class code for this device. This code has the
value 06h, indicating a bridge device.
Sub-Class Code (SUBCC):
Indicates the sub-class code for this device. The code is 04h
indicating a PCI-to-PCI bridge.
Programming Interface (PI):
Indicates the programming interface of this device. This value
does not specify a particular register set layout and provides no
practical use for this device.
Cache Line Size (Scratch Pad):
Implemented by PCI Express* devices as a read-write field for
legacy compatibility purposes but has no impact on any PCI
Express device functionality.
PCI Express Graphics Device 1 Configuration Registers (D1:F0)
0/1/0/PCI
9-Bh
060400h
RO
24 bits
0/1/0/PCI
0Ch
00h
R/W
8 bits
Description
Description
Datasheet