QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 243

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

PCI Express Graphics Device 1 Configuration Registers (D1:F0)
7.1.23
Datasheet
PM_CAPID1 - Power Management Capabilities
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
31:27
26:26
25:25
24:22
21:21
20:20
19:19
18:16
15:8
7:0
Bit
Access
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Default
Value
000b
010b
19h
90h
01h
0b
0b
0b
0b
0b
PME Support (PMES):
This field indicates the power states in which this device may
indicate PME wake via PCI Express messaging. D0, D3hot &
D3cold. This device is not required to do anything to support
D3hot & D3cold; it simply must report that those states are
supported. Refer to the current PCI Power Management
Specification for encoding explanation and other power
management details.
D2 Power State Support (D2PSS):
Hardwired to 0 to indicate that the D2 power management state
is not supported.
D1 Power State Support (D1PSS):
Hardwired to 0 to indicate that the D1 power management state
is not supported.
Auxiliary Current (AUXC):
Hardwired to 0 to indicate that there are no 3.3Vaux auxiliary
current requirements.
Device Specific Initialization (DSI):
Hardwired to 0 to indicate that special initialization of this device
is not required before generic class device driver is to use it.
Auxiliary Power Source (APS):
Hardwired to 0.
PME Clock (PMECLK):
Hardwired to 0 to indicate this device does not support PMEB
generation.
PCI PM CAP Version (PCIPMCV):
Hardwired to 02h to indicate there are 4 bytes of power
management registers implemented and that this device complies
with the current PCI Power Management Interface Specification.
Pointer to Next Capability (PNC):
This contains a pointer to the next item in the capabilities list. If
MSICH (CAPL[0] @ 7Fh) is 0, then the next item in the
capabilities list is the Message Signaled Interrupts (MSI)
capability at 90h. If MSICH (CAPL[0] @ 7Fh) is 1, then the next
item in the capabilities list is the PCI Express capability at A0h.
Capability ID (CID):
Value of 01h identifies this linked list item (capability structure)
as being for PCI Power Management registers.
0/1/0/PCI
80-83h
C8029001h
RO
32 bits
Description
243