QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 141

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

Device 0 Memory Mapped I/O Register
6.2.25
Datasheet
C0DMC - Channel 0 DRAM Maintenance Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
The register fields allow control of DRAM and MCH ODT.
28:25
24:22
18:16
15:8
7:0
Bit
31
30
29
21
20
19
Access
R/W/L
R/W/L
R/W/L
R/W/L
R/W/L
R/W/L
R/W/L
R/L
RO
RO
RO
Default
Value
000b
000b
00h
00h
0b
0b
0b
0h
0b
0b
0b
Dram Throttle Lock (DTLOCK):
This bit secures the Dram throttling control registers DT*EW and
DTC. This bit defaults to 0. Once a 1 is written to this bit, all of
the configuration register bits are read-only.
Reserved
Reserved
Reserved
Reserved
(G)MCH Bandwidth-Based Throttling Enable:
0 = Bandwidth Threshold (WAB) is not used for throttling.
1 = Bandwidth Threshold (WAB) is used for throttling.
If both bandwidth-based and thermal sensor-based throttling
modes are on and the thermal sensor trips, thermal threshold is
used for throttling.
(G)MCH Thermal Sensor Trip Enable:
0 = (G)MCH throttling is not initiated when the (G)MCH thermal
sensor trips.
1 = (G)MCH throttling is initiated when the (G)MCH thermal
sensor trips and the filter output is equal to or exceeds thermal
threshold WAT.
Reserved
Time Constant:
000: 2^28 Clocks
001: 2^29 Clocks
010: 2^30 Clocks
011: 2^31 Clocks
1XX: Reserved
WAB:
Threshold allowed per clock for bandwidth based throttling.
(G)MCH does not allow transactions to proceed on the DDR bus
if the output of the filter equals or exceeds this value.
WAT:
Threshold allowed per clock during for thermal sensor enabled
throttling. (G)MCH does not allow transactions to proceed on the
DDR bus if the output of the filter equals or exceeds this value.
0/0/0/MCHBAR
164-167h
00000020h
R/W; RO
32 bits
Description
141