QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 245

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

PCI Express Graphics Device 1 Configuration Registers (D1:F0)
Datasheet
1:0
Bit
Access
R/W
Default
Value
00b
Power State (PS): Indicates the current power state of this
device and can be used to set the device into a new power state.
If software attempts to write an unsupported state to this field,
write operation must complete normally on the bus, but the data
is discarded and no state change occurs.
Support of D3cold does not require any special action.
While in the D3hot state, this device can only act as the target of
PCI configuration transactions (for power management control).
This device also cannot generate interrupts or respond to MMR
cycles in the D3 state. The device must return to the D0 state in
order to be fully-functional.
When the Power State is other than D0, the bridge will Master
Abort (i.e., not claim) any downstream cycles (with exception of
type 0 configuration cycles). Consequently, these unclaimed
cycles will go down DMI and come back up as Unsupported
Requests, which the MCH logs as Master Aborts in Device 0
PCISTS[13]
There is no additional hardware functionality required to support
these Power States.
00:
01:
10:
11:
D0
D1 (Not supported in this device)
D2 (Not supported in this device)
D3
Description
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