QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 36

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

2.1
2.1.1
36
Host Interface
Unless otherwise noted, the voltage level for all signals in this interface is tied to the
termination voltage of the host bus (V
Host Interface Signals
HADS#
HBNR#
HBPRI#
HBREQ0#
HCPURST#
HDBSY#
HDEFER#
Signal Name
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
Type
I/O
I/O
I/O
I/O
O
O
O
Host Address Strobe:
The system bus owner asserts HADS# to indicate the first of two
cycles of a request phase. The (G)MCH can also assert this signal
for snoop cycles and interrupt messages.
Host Block Next Request:
Used to block the current request bus owner from issuing a new
request. This signal is used to dynamically control the CPU bus
pipeline depth.
Host Bus Priority Request:
The (G)MCH is the only Priority Agent on the system bus. It
asserts this signal to obtain the ownership of the address bus.
This signal has priority over symmetric bus requests and will
cause the current symmetric owner to stop issuing new
transactions unless the HLOCK# signal was asserted.
Host Bus Request 0#:
The (G)MCH pulls the processor bus HBREQ0# signal low during
HCPURST#. The signal is sampled by the processor on the
active-to-inactive transition of HCPURST#.
HBREQ0# should be tri-stated after the hold time requirement
has been satisfied.
Host CPU Reset:
The CPURST# pin is an output from the (G)MCH. The (G)MCH
asserts HCPURST# while RSTIN# is asserted and for
approximately 1 ms after RSTIN# is deasserted.
HCPURST# allows the processor to begin execution in a known
state.
Host Data Bus Busy:
Used by the data bus owner to hold the data bus for transfers
requiring more than one cycle.
Host Defer:
Signals that the (G)MCH will terminate the transaction currently
being snooped with either a deferred response or with a retry
response.
CCP
).
Description
Signal Description
Datasheet