QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 283

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

Internal Graphics Device 2 Configuration Register (D2:F0-F1)
8.1.12
8.1.13
Datasheet
GMADR - Graphics Memory Range Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
IGD graphics memory base address is specified in this register.
GTTADR - Graphics Translation Table Range Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register requests allocation for Graphics Translation Table Range. The allocation is
for 256 KB and the base address is defined by bits [31:18].
31:28
31:18
27:4
17:4
2:1
2:1
Bit
Bit
3
0
3
0
Access
Access
R/W
R/W
RO
RO
RO
RO
RO
RO
RO
RO
000000h
Default
Default
0000h
0000h
Value
Value
000b
00b
00b
0b
0b
1b
0b
Memory Base Address:
Set by the OS, these bits correspond to address signals [31:18].
Address Mask:
Hardwired to 0’s to indicate at least 256-KB address range.
Prefetchable Memory:
Hardwired to 0 to prevent prefetching.
Memory Type:
Hardwired to 0’s to indicate 32-bit address.
Memory/IO Space:
Hardwired to 0 to indicate memory space.
Memory Base Address:
Set by the OS, these bits correspond to address signals [31:28].
Address Mask:
Hardwired to 0’s to indicate at least 256-MB address range
Prefetchable Memory:
Hardwired to 1 to enable prefetching
Memory Type:
Hardwired to 0 to indicate 32-bit address.
Memory/IO Space:
Hardwired to 0 to indicate memory space.
0/2/0/PCI
18-1Bh
00000008h
R/W; ROR/W/L;
32 bits
0/2/0/PCI
1C-1Fh
00000000h
R/W; R/W/L; RO
32 bits
Description
Description
283