QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 415

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

Strapping Configuration
12
Table 56.
Datasheet
Strapping Configuration
Mobile Intel 945GM/GME/PM/GMS/GU/GSE, 943/940GML and Intel 945GT
Express Chipset Strapping Signals and Configuration
NOTES:
1.
CFG[2:0]
CFG[4:3]
CFG5
CFG6
CFG7
CFG8
CFG9
CFG[11:10]
CFG[13:12]
CFG[15:14]
CFG16
CFG17
SDVO_CTRLDATA
CFG[18]
CFG[19]
CFG[20]
Pin Name
All strap signals are sampled with respect to the leading edge of the (G)MCH Power OK
(PWROK) signal
FSB Frequency
Select
Reserved
DMI X2 Select
Reserved
CPU Strap
Reserved
PCI Express*
Graphics Lane
Reversal
Reserved
XOR/ALLZ
Reserved
FSB Dynamic ODT
Reserved
SDVO Present
VCC Select
DMI Lane Reversal
SDVO/PCIe
concurrent
Strap Description
000 = FSB400 (Ultra Mobile only)
001 = FSB533
011 = FSB667
Others = Reserved
0 = DMI X2
1 = DMI X4 (Default)
0 = Reserved
1 = Mobile CPU (Default)
0 = Reverse Lanes, 15->0, 14->1 etc…
1 = Normal operation (Default): Lane
00 = Partial Clock Gating Disable
01 = XOR Mode Enabled
10 = All-Z Mode Enabled
11 = Normal Operation (Default)
0 = Dynamic ODT Disabled
1 = Dynamic ODT Enabled (Default)
0 = No SDVO Card Present (Default)
1 = SDVO Card Present
0 = 1.05 V (Default)
1 = 1.5 V
0 = Normal operation (Default): Lane
1 = Reverse Lanes, 3->0, 2->1 etc
Note: Mobile Intel® 945GMS/GSE
Express Chipset does not support DMI
lane reversal
0 = Only SDVO or PCIE x1 is
operational (Default)
1 = SDVO and PCIE x1 are operating
simultaneously via the PEG port
Numbered in Order
Numbered in Order
Configuration
1,2
1,2
1,2,3
1,2
1
1,3
1
1
1,2
1
1,2
1,3
Notes
415