QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 378

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

10.5.4.2.2
10.5.4.2.3
Figure 22.
378
LVDS Interface Signals
LVDS for flat panel is compatible with the ANSI/TIA/EIA-644 specification. This is an
electrical standard only defining driver output characteristics and receiver input
characteristics. There are two LVDS transmitter channels (channel A and channel B) in
the LVDS interface. Each channel consists of 3-data pairs and a clock pair. The interface
consists of a total of eight differential signal pairs of which six are data and two are
clocks. The phase locked transmit clock is transmitted in parallel with the data being
sent out over the data pairs and over the LVDS clock pair.
Each channel supports transmit clock frequency ranges from 25 MHz to 112 MHz, which
provides a throughput of up to 784 Mbps on each data output and up to 112 MP/s on
the input. When using both channels, they each operate at the same frequency each
carrying a portion of the data. The maximum pixel rate is increased to 224 MP/s but
may be limited to less than that due to restrictions elsewhere in the circuit.
The LVDS Port enable bit enables or disables the entire LVDS interface. When the port
is disabled, it will be in a low power state. Once the port is enabled, individual driver
pairs will be disabled based on the operating mode. Disabled drivers can be powered
down for reduced power consumption or optionally fixed to forced 0’s output.
LVDS Data Pairs and Clock Pairs
The LVDS data and clock pairs are identical buffers and differ only in the use defined for
that pair. The LVDS data pair is used to transfer pixel data as well as the LCD timing
control signals. The pixel bus data to serial data mapping options are specified
elsewhere. A single- or dual-clock pair is used to transfer clocking information to the
LVDS receiver. A serial pattern of 1100011 represents one cycle of the clock.
There are two LVDS transmitter channels (channel A and channel B) in the LVDS
interface. Each channel contains 1 clock pair and 3-data pair of low voltage differential
swing signals.
LVDS Signals and Swing Voltage
1’s and 0’s are represented the differential voltage between the pair of signals.
Figure 22
shows a pair of LVDS signals and swing voltage.
Functional Description
Datasheet