QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 291

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

Internal Graphics Device 2 Configuration Register (D2:F0-F1)
8.1.27
8.1.28
Datasheet
CAPL - Capabilities List Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register allows BIOS to hide capabilities that are part of the Device 2 PCI
Capabilities Linked List. By setting the appropriate bits, certain capabilities will be
“skipped” during a later phase of system initialization.
GDRST - Graphics Debug Reset
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
7:1
7:2
Bit
Bit
0
1
Access
Access
R/W
RO
RO
RO
Default
Default
Value
Value
00h
00h
0b
0b
Reserved
MSI Capability Hidden (MSICH):
0: MSI Capability at 90h is included in list.
1: MSI Capability is not included in list. Power Management
Capability ID's (D0h) pointer is the next capability.
Reserved
Graphics Reset Status:
Reset.
This bit gets is set to a 1 when Graphics debug reset bit is set to a
1 and the Graphics hardware has completed the debug reset
sequence and all Graphics assets are in reset. This bit is cleared
when Graphics Debug Reset bit is set to a 0.
0: Graphics subsystem not in Reset.
1: Graphics Subsystem in Reset as a result of Graphics Debug
0/2/0/PCI
7Fh
00h
R/W; RO
8 bits
0/2/0/PCI
C0h
00h
R/W; RO
8 bits
Description
Description
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