QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 296

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

8.1.34
8.1.35
Note:
296
ASLE - System Display Event Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
The exact use of these bytes including whether they are addressed as bytes, words, or
as a dword, is not pre-determined but subject to change by driver and System BIOS
teams (acting in unison).
GCFC - Graphics Clock Frequency Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
The values indicated in this register are applicable only for the Mobile Intel 945GM/
GME/GMS/GU/GSE, 943/940GML and Intel 945GT Express Chipset. This register is a
“Don’t Care” for the Mobile Intel 945PM Express Chipset.
31:24
23:16
15:8
7:0
Bit
Access
R/W
R/W
R/W
R/W
Default
Value
N/A
N/A
N/A
N/A
ASLE Scratch Trigger3:
When written, this scratch byte triggers an interrupt when IEF bit
0 is enabled and IMR bit 0 is unmasked. If written as part of a 16-
bit or 32-bit write, only one interrupt is generated in common.
ASLE Scratch Trigger2:
When written, this scratch byte triggers an interrupt when IEF bit
0 is enabled and IMR bit 0 is unmasked. If written as part of a 16-
bit or 32-bit write, only one interrupt is generated in common.
ASLE Scratch Trigger 1:
When written, this scratch byte triggers an interrupt when IEF bit
0 is enabled and IMR bit 0 is unmasked. If written as part of a 16-
bit or 32-bit write, only one interrupt is generated in common.
ASLE Scratch Trigger 0:
When written, this scratch byte triggers an interrupt when IEF bit
0 is enabled and IMR bit 0 is unmasked. If written as part of a 16-
bit or 32-bit write, only one interrupt is generated in common.
Internal Graphics Device 2 Configuration Register (D2:F0-F1)
0/2/0/PCI
E4-E7h
R/W
32 bits
0/2/0/PCI
F0-F1h
0000h
R/W; RO
16 bits
Description
Datasheet