QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 202

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

6.6.4
6.6.5
202
DMIPVCCTL - DMI Port VC Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
DMIVC0RCAP - DMI VC0 Resource Capability
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
31:24
22:16
15:4
14:8
3:1
7:0
Bit
Bit
23
15
0
Access
Access
R/W
RO
RO
RO
RO
RO
RO
RO
RO
Default
Default
Value
Value
000h
000b
00h
00h
00h
01h
0b
0b
0b
Reserved
VC Arbitration Select (VCAS):
This field will be programmed by software to the only possible
value as indicated in the VC Arbitration Capability field.
The value 000b when written to this field will indicate the VC
arbitration scheme is hardware fixed (in the root complex).
This field cannot be modified when more than one VC in the
LPVC group is enabled.
000: Hardware fixed arbitration scheme - e.g., Round Robin
Others: Reserved
See the current PCI Local Bus Specification for more details.
Reserved
Reserved
Reserved
Reserved
Reject Snoop Transactions (REJSNPT):
the TLP header are allowed on this VC.
TLP header will be rejected as an Unsupported Request.
Reserved
Port Arbitration Capability (PAC):
Having only bit 0 set indicates that the only supported
arbitration scheme for this VC is non-configurable hardware-
fixed.
0: Transactions with or without the No Snoop bit set within
1: Any transaction without the No Snoop bit set within the
0/0/0/DMIBAR
C-Dh
0000h
R/W; RO
16 bits
0/0/0/DMIBAR
10-13h
00000001h
RO
32 bits
Description
Description
Device 0 Memory Mapped I/O Register
Datasheet