QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 326

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

9.2.2
9.2.3
Table 18.
9.3
Note:
326
TSEG
TSEG is optionally 1 MB, 2 MB, or 8 MB in size. TSEG is below IGD stolen memory,
which is at the top of physical memory. SMM-mode CPU accesses to enabled TSEG
access the physical DRAM at the same address. Non-CPU originated accesses are not
allowed to SMM space. PCI Express, DMI, and Internal Graphics originated cycles to
enabled SMM space are handled as invalid cycle type with reads and writes to location 0
and byte enables turned off for writes. When the extended SMRAM space is enabled,
CPU accesses to the TSEG range without SMM attribute or without WB attribute are also
forwarded to memory as invalid accesses (see
cycles that target TSEG space are completed to DRAM for cache coherency. When SMM
is enabled the maximum amount of memory available to the system is equal to the
amount of physical DRAM minus the value in the TSEG register which is fixed at 1 MB,
2 MB or 8 MB.
Pre-allocated Memory
Voids of physical addresses that are not accessible as general system memory and
reside within system memory address range (< TOLUD) are created for SMM-mode and
legacy VGA graphics compatibility. It is the responsibility of BIOS to properly
initialize these regions.
How to enable and disable these ranges are described in the (G)MCH Control Register
Device 0 (GGC).
Pre-allocated Memory Example for 64-MB DRAM, 1-MB VGA,
and 1-MB TSEG
PCI Memory Address Range (TOLUD – 4 GB)
This address range, from the top of physical memory to 4 GB (top of addressable
memory space supported by the (G)MCH) is normally mapped to the DMI Interface.
Exceptions to this mapping include the BAR memory mapped regions, which include:
EPBAR, MCHBAR, DMIBAR.
In the PCI Express port, there are two exceptions to this rule:
AGP Aperture no longer exists with PCI Express.
0000_0000h – 03DF_FFFFh
03E0_0000h – 03EF_FFFFh
03F0_0000h – 03FF_FFFFh
Memory Segments
— Addresses decoded to the PCI Express Memory Window defined by the
— Addresses decoded to PCI Express Configuration Space are mapped based on
MBASE1, MLIMIT1, PMBASE1, and PMLIMIT1 registers are mapped to PCI
Express.
Bus, Device, and Function number. (PCIEXBAR range).
Table 18
SMM Mode Only - CPU
Attributes
details the location and attributes of the regions.
Reads
R/W
R/W
Table
19). Non-SMM-mode Write Back
TSEG Address Range & Pre-
allocated Memory
Pre-allocated Graphics VGA
memory.
1 MB (or 4/8/16/32/64 MB) when
IGD is enabled
Available System Memory 62 MB
Comments
System Address Map
Datasheet